soc/amd/picasso: Add MADT entry for GNB IOAPIC
Add the missing entry using new Kconfig symbol for IOAPIC ID. coreboot will always enable the GNB IOAPIC. Cq-Depend: chrome-internal:3247431, chrome-internal:3253044 BUG=b:167421913, b:166519072 TEST=Boot fully to morphius board with and without amd_iommu kernel parameter. Dump MADT and IVRS tables. Cross check ioapic entries in MADT against IVRS. BRANCH=Zork Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Change-Id: Ic4a2e9b71dba948e8a4907e5f97131426d8a4a3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/45056 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -49,10 +49,12 @@ unsigned long acpi_fill_madt(unsigned long current)
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/* create all subtables for processors */
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current = acpi_create_madt_lapics(current);
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/* Write IOAPIC, only one */
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current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current,
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CONFIG_PICASSO_FCH_IOAPIC_ID, IO_APIC_ADDR, 0);
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current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current,
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CONFIG_PICASSO_GNB_IOAPIC_ID, GNB_IO_APIC_ADDR, IO_APIC_INTERRUPTS);
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/* 0: mean bus 0--->ISA */
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/* 0: PIC 0 */
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/* 2: APIC 2 */
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