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nb/intel/gm45: Factor out {DMI,EP,MCH}BAR accessors 

These accessors can be reused for several other northbridges.

Tested with BUILD_TIMELESS=1, Roda RK9 remains identical.

Change-Id: Ia16ccc63dddebf938f4e9a7f5518e4d25d3e7e66
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49748
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2021-01-20 00:36:31 +01:00
parent dd1fb4e38c
commit f462b3d379
10 changed files with 61 additions and 26 deletions
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1
src/Kconfig
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@ -523,6 +523,7 @@ comment "CPU"
source "src/cpu/Kconfig"
comment "Northbridge"
source "src/northbridge/*/*/Kconfig"
source "src/northbridge/*/*/Kconfig.common"
comment "Southbridge"
source "src/southbridge/*/*/Kconfig"
comment "Super I/O"

17
src/northbridge/intel/common/Kconfig.common Normal file
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@ -0,0 +1,17 @@
# SPDX-License-Identifier: GPL-2.0-only
config NORTHBRIDGE_INTEL_COMMON
bool
if NORTHBRIDGE_INTEL_COMMON
config FIXED_DMIBAR_MMIO_BASE
hex
config FIXED_EPBAR_MMIO_BASE
hex
config FIXED_MCHBAR_MMIO_BASE
hex
endif # NORTHBRIDGE_INTEL_COMMON

24
src/northbridge/intel/common/fixed_bars.h Normal file
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@ -0,0 +1,24 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef NORTHBRIDGE_INTEL_COMMON_FIXED_BARS_H
#define NORTHBRIDGE_INTEL_COMMON_FIXED_BARS_H
_Static_assert(CONFIG_FIXED_MCHBAR_MMIO_BASE != 0, "MCHBAR base address is zero");
_Static_assert(CONFIG_FIXED_DMIBAR_MMIO_BASE != 0, "DMIBAR base address is zero");
_Static_assert(CONFIG_FIXED_EPBAR_MMIO_BASE != 0, "EPBAR base address is zero");
#include <stdint.h>
#define MCHBAR8(x) (*((volatile u8 *)(CONFIG_FIXED_MCHBAR_MMIO_BASE + (x))))
#define MCHBAR16(x) (*((volatile u16 *)(CONFIG_FIXED_MCHBAR_MMIO_BASE + (x))))
#define MCHBAR32(x) (*((volatile u32 *)(CONFIG_FIXED_MCHBAR_MMIO_BASE + (x))))
#define DMIBAR8(x) (*((volatile u8 *)(CONFIG_FIXED_DMIBAR_MMIO_BASE + (x))))
#define DMIBAR16(x) (*((volatile u16 *)(CONFIG_FIXED_DMIBAR_MMIO_BASE + (x))))
#define DMIBAR32(x) (*((volatile u32 *)(CONFIG_FIXED_DMIBAR_MMIO_BASE + (x))))
#define EPBAR8(x) (*((volatile u8 *)(CONFIG_FIXED_EPBAR_MMIO_BASE + (x))))
#define EPBAR16(x) (*((volatile u16 *)(CONFIG_FIXED_EPBAR_MMIO_BASE + (x))))
#define EPBAR32(x) (*((volatile u32 *)(CONFIG_FIXED_EPBAR_MMIO_BASE + (x))))
#endif /* ! NORTHBRIDGE_INTEL_COMMON_FIXED_BARS_H */

9
src/northbridge/intel/gm45/Kconfig
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@ -43,4 +43,13 @@ config INTEL_GMA_BCLV_OFFSET
config INTEL_GMA_BCLM_OFFSET
default 0x61256
config FIXED_MCHBAR_MMIO_BASE
default 0xfed14000
config FIXED_DMIBAR_MMIO_BASE
default 0xfed18000
config FIXED_EPBAR_MMIO_BASE
default 0xfed19000
endif

7
src/northbridge/intel/gm45/acpi/gm45.asl
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@ -1,7 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include "hostbridge.asl"
#include "../memmap.h"
#include <southbridge/intel/i82801ix/i82801ix.h>
/* PCI Device Resource Consumption */
@ -14,9 +13,9 @@ Device (PDRC)
// now.
Name (PDRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH)
Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000)
Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00004000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000)
Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH

6
src/northbridge/intel/gm45/early_init.c
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@ -10,13 +10,13 @@ void gm45_early_init(void)
const pci_devfn_t d0f0 = PCI_DEV(0, 0, 0);
/* Setup MCHBAR. */
pci_write_config32(d0f0, D0F0_MCHBAR_LO, DEFAULT_MCHBAR | 1);
pci_write_config32(d0f0, D0F0_MCHBAR_LO, CONFIG_FIXED_MCHBAR_MMIO_BASE | 1);
/* Setup DMIBAR. */
pci_write_config32(d0f0, D0F0_DMIBAR_LO, DEFAULT_DMIBAR | 1);
pci_write_config32(d0f0, D0F0_DMIBAR_LO, CONFIG_FIXED_DMIBAR_MMIO_BASE | 1);
/* Setup EPBAR. */
pci_write_config32(d0f0, D0F0_EPBAR_LO, DEFAULT_EPBAR | 1);
pci_write_config32(d0f0, D0F0_EPBAR_LO, CONFIG_FIXED_EPBAR_MMIO_BASE | 1);
pci_write_config32(d0f0, D0F0_PMBASE, DEFAULT_PMBASE | 1);

12
src/northbridge/intel/gm45/gm45.h
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@ -218,9 +218,7 @@ enum {
* MCHBAR
*/
#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x))))
#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x))))
#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x))))
#include <northbridge/intel/common/fixed_bars.h>
#define HPLLVCO_MCHBAR 0x0c0f
@ -342,10 +340,6 @@ enum {
* DMIBAR
*/
#define DMIBAR8(x) (*((volatile u8 *)(DEFAULT_DMIBAR + (x))))
#define DMIBAR16(x) (*((volatile u16 *)(DEFAULT_DMIBAR + (x))))
#define DMIBAR32(x) (*((volatile u32 *)(DEFAULT_DMIBAR + (x))))
#define DMIVCECH 0x000 /* 32bit */
#define DMIPVCCAP1 0x004 /* 32bit */
@ -374,10 +368,6 @@ enum {
* EPBAR
*/
#define EPBAR8(x) (*((volatile u8 *)(DEFAULT_EPBAR + (x))))
#define EPBAR16(x) (*((volatile u16 *)(DEFAULT_EPBAR + (x))))
#define EPBAR32(x) (*((volatile u32 *)(DEFAULT_EPBAR + (x))))
#define EPPVCCAP1 0x004 /* 32bit */
#define EPPVCCTL 0x00c /* 32bit */

4
src/northbridge/intel/gm45/memmap.h
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@ -3,10 +3,6 @@
#ifndef __NORTHBRIDGE_INTEL_GM45_MEMMAP_H__
#define __NORTHBRIDGE_INTEL_GM45_MEMMAP_H__
#define DEFAULT_MCHBAR 0xfed14000
#define DEFAULT_DMIBAR 0xfed18000
#define DEFAULT_EPBAR 0xfed19000
#define IOMMU_BASE1 0xfed90000
#define IOMMU_BASE2 0xfed91000
#define IOMMU_BASE3 0xfed92000

4
src/northbridge/intel/gm45/pcie.c
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@ -251,7 +251,7 @@ static void setup_rcrb(const int peg_enabled)
/* Link1: component ID 1, link valid. */
EPBAR32(EPLE1D) = (EPBAR32(EPLE1D) & 0xff000000) | (1 << 16) | (1 << 0);
EPBAR32(EPLE1A) = DEFAULT_DMIBAR;
EPBAR32(EPLE1A) = CONFIG_FIXED_DMIBAR_MMIO_BASE;
if (peg_enabled)
/* Link2: link_valid. */
@ -269,7 +269,7 @@ static void setup_rcrb(const int peg_enabled)
/* Link2: component ID 1 (MCH), link valid */
DMIBAR32(DMILE2D) =
(DMIBAR32(DMILE2D) & 0xff000000) | (1 << 16) | (1 << 0);
DMIBAR32(DMILE2A) = DEFAULT_MCHBAR;
DMIBAR32(DMILE2A) = CONFIG_FIXED_MCHBAR_MMIO_BASE;
}
void gm45_late_init(const stepping_t stepping)

3
src/southbridge/intel/i82801ix/dmi_setup.c
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@ -2,7 +2,6 @@
#include <device/pci_def.h>
#include <console/console.h>
#include <northbridge/intel/gm45/gm45.h>
#include "i82801ix.h"
/* VC1 Port Arbitration Table */
@ -67,7 +66,7 @@ void i82801ix_dmi_setup(void)
RCBA8(RCBA_ULD + 3) = 1;
RCBA8(RCBA_ULD + 2) = 1;
/* Set target rcrb base address, i.e. DMIBAR. */
RCBA32(RCBA_ULBA) = (uintptr_t)DEFAULT_DMIBAR;
RCBA32(RCBA_ULBA) = (uintptr_t)CONFIG_FIXED_DMIBAR_MMIO_BASE;
/* Enable ASPM. */
if (LPC_IS_MOBILE(PCI_DEV(0, 0x1f, 0))) {