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slippy/falco/peppy: Route USB to XHCI on resume 

Turn on the pei_data flag that will instruct the reference code
binary to route all USB ports to the XHCI controller on resume and
disable the EHCI controller(s).

Change-Id: I2f2ed853a6d17f90ea524bc516f3e78079222739
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/63798
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4404
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
Duncan Laurie 2013-07-30 15:43:43 -07:00 committed by Patrick Georgi
parent 289bac6a04
commit f47c4bcd01
3 changed files with 3 additions and 0 deletions
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1
src/mainboard/google/falco/romstage.c
View File

@ -132,6 +132,7 @@ void mainboard_romstage_entry(unsigned long bist)
// Enable 2x refresh mode
ddr_refresh_2x: 1,
max_ddr3_freq: 1600,
usb_xhci_on_resume: 1,
usb2_ports: {
/* Length, Enable, OCn#, Location */
{ 0x0064, 1, 0, /* P0: Port A, CN8 */

1
src/mainboard/google/peppy/romstage.c
View File

@ -143,6 +143,7 @@ void mainboard_romstage_entry(unsigned long bist)
dimm_channel0_disabled: 2,
dimm_channel1_disabled: 2,
max_ddr3_freq: 1600,
usb_xhci_on_resume: 1,
usb2_ports: {
/* Length, Enable, OCn#, Location */
{ 0x0150, 1, USB_OC_PIN_SKIP, /* P0: LTE */

1
src/mainboard/google/slippy/romstage.c
View File

@ -158,6 +158,7 @@ void mainboard_romstage_entry(unsigned long bist)
dimm_channel0_disabled: 2,
dimm_channel1_disabled: 2,
max_ddr3_freq: 1600,
usb_xhci_on_resume: 1,
usb2_ports: {
/* Length, Enable, OCn#, Location */
{ 0x0150, 1, USB_OC_PIN_SKIP, /* P0: LTE */