From f47e85fc7211494f501b5c9717a443e5b781b58d Mon Sep 17 00:00:00 2001 From: Scott Chao Date: Wed, 22 Nov 2023 14:52:14 +0800 Subject: [PATCH] mb/google/nissa: make GPP_F17 edge triggered to avoid spamming EC In nissa platform, we configured GPP_F17 as SCI+APIC to wake the system and also generate IRQ to the IOAPIC. Currently, we set GPP_F17 to level triggered and it causes AP (Application Processor) to keep sending GET_NEXT_EVENT to EC during resume from suspend by connecting AC. So we change GPP_F17 to edge triggered to avoid this condition. BUG=b:308716748 TEST=Original failure rate was 7 out of 10 times and it reduced to 0 out of 60 times on six joxer systems. Signed-off-by: Scott Chao Change-Id: I3ceb1dfce46376a6a9a8c6cb6d691d818a0a42ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/79244 Reviewed-by: Subrata Banik Reviewed-by: Eric Lai Tested-by: build bot (Jenkins) Reviewed-by: Reka Norman Reviewed-by: Paul Menzel --- src/mainboard/google/brya/variants/baseboard/nissa/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c b/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c index 781f00add5..5d83e7a103 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c @@ -242,7 +242,7 @@ static const struct pad_config gpio_table[] = { /* F16 : NC */ PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG), /* F17 : THC1_SPI2_RST# ==> EC_SOC_WAKE_ODL */ - PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F17, NONE, LEVEL, INVERT, LOCK_CONFIG), + PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F17, NONE, EDGE_SINGLE, INVERT, LOCK_CONFIG), /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ PAD_CFG_GPI_LOCK(GPP_F18, NONE, LOCK_CONFIG), /* F19 : Not available */