ipq8064: Make timer code compile
Commment out nonessential timer services and modify the source code to cleanly build in coeboot environment. Do not remove dead code just yet, these functions might be necessary later. Need to rename the soc timer.h to prevent collisions with timer.h in the top level include directory. Currently build timer code for ramstage only. BUG=chrome-os-partner:27784 TEST='emerge-storm coreboot' still succeeds Original-Change-Id: Ib10133ccb42697840708845a8ea6d75ceeaeb3d5 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/194067 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 987ce95220953c16216d1e1d70d5a941d05fc9bc) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia9cf175da11c70709354def5e51bf79df4fda2fe Reviewed-on: http://review.coreboot.org/7269 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
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@ -6,6 +6,7 @@ romstage-y += gpio.c
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ramstage-y += cbfs.c
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ramstage-y += cbfs.c
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ramstage-y += gpio.c
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ramstage-y += gpio.c
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ramstage-y += timer.c
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ifeq ($(CONFIG_USE_BLOBS),y)
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ifeq ($(CONFIG_USE_BLOBS),y)
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@ -24,12 +24,3 @@ int init_default_cbfs_media(struct cbfs_media *media)
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{
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{
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return 0;
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return 0;
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}
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}
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/*
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* Temporary change to make sure storm code still builds. Will be dropped
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* shortly.
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*/
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#include <delay.h> /* This driver serves as a CBFS media source. */
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void init_timer(void)
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{
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}
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@ -4,9 +4,23 @@
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#ifndef _IPQ806X_CDP_H_
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#ifndef _IPQ806X_CDP_H_
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#define _IPQ806X_CDP_H_
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#define _IPQ806X_CDP_H_
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#include <phy.h>
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unsigned smem_get_board_machtype(void);
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unsigned int smem_get_board_machtype(void);
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typedef enum {
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PHY_INTERFACE_MODE_MII,
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PHY_INTERFACE_MODE_GMII,
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PHY_INTERFACE_MODE_SGMII,
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PHY_INTERFACE_MODE_QSGMII,
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PHY_INTERFACE_MODE_TBI,
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PHY_INTERFACE_MODE_RMII,
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PHY_INTERFACE_MODE_RGMII,
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PHY_INTERFACE_MODE_RGMII_ID,
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PHY_INTERFACE_MODE_RGMII_RXID,
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PHY_INTERFACE_MODE_RGMII_TXID,
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PHY_INTERFACE_MODE_RTBI,
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PHY_INTERFACE_MODE_XGMII,
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PHY_INTERFACE_MODE_NONE /* Must be last */
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} phy_interface_t;
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typedef struct {
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typedef struct {
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unsigned int gpio;
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unsigned int gpio;
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@ -73,17 +87,17 @@ typedef struct {
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} spinorflash_params_t;
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} spinorflash_params_t;
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typedef struct {
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typedef struct {
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uint count;
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unsigned count;
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u8 addr[7];
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uint8_t addr[7];
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} ipq_gmac_phy_addr_t;
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} ipq_gmac_phy_addr_t;
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typedef struct {
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typedef struct {
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uint base;
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unsigned base;
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int unit;
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int unit;
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uint is_macsec;
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unsigned is_macsec;
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uint mac_pwr0;
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unsigned mac_pwr0;
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uint mac_pwr1;
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unsigned mac_pwr1;
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uint mac_conn_to_phy;
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unsigned mac_conn_to_phy;
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phy_interface_t phy;
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phy_interface_t phy;
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ipq_gmac_phy_addr_t phy_addr;
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ipq_gmac_phy_addr_t phy_addr;
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} ipq_gmac_board_cfg_t;
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} ipq_gmac_board_cfg_t;
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@ -98,6 +112,7 @@ typedef struct {
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unsigned int uart_gsbi_base;
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unsigned int uart_gsbi_base;
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unsigned int uart_dm_base;
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unsigned int uart_dm_base;
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unsigned int clk_dummy;
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unsigned int clk_dummy;
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#if 0
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uart_clk_mnd_t mnd_value;
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uart_clk_mnd_t mnd_value;
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unsigned int gmac_gpio_count;
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unsigned int gmac_gpio_count;
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gpio_func_data_t *gmac_gpio;
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gpio_func_data_t *gmac_gpio;
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@ -105,10 +120,12 @@ typedef struct {
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flash_desc flashdesc;
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flash_desc flashdesc;
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spinorflash_params_t flash_param;
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spinorflash_params_t flash_param;
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gpio_func_data_t dbg_uart_gpio[NO_OF_DBG_UART_GPIOS];
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gpio_func_data_t dbg_uart_gpio[NO_OF_DBG_UART_GPIOS];
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#endif
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} __attribute__ ((__packed__)) board_ipq806x_params_t;
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} __attribute__ ((__packed__)) board_ipq806x_params_t;
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extern board_ipq806x_params_t *gboard_param;
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extern board_ipq806x_params_t *gboard_param;
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#if 0
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static inline int gmac_cfg_is_valid(ipq_gmac_board_cfg_t *cfg)
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static inline int gmac_cfg_is_valid(ipq_gmac_board_cfg_t *cfg)
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{
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{
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/*
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/*
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@ -121,7 +138,8 @@ static inline int gmac_cfg_is_valid(ipq_gmac_board_cfg_t *cfg)
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(cfg < &gboard_param->gmac_cfg[IPQ_GMAC_NMACS]) &&
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(cfg < &gboard_param->gmac_cfg[IPQ_GMAC_NMACS]) &&
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(cfg->unit >= 0) && (cfg->unit < IPQ_GMAC_NMACS));
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(cfg->unit >= 0) && (cfg->unit < IPQ_GMAC_NMACS));
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}
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}
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#endif
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unsigned int get_board_index(unsigned int machid);
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void ipq_configure_gpio(gpio_func_data_t *gpio, uint count);
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unsigned int get_board_index(unsigned machid);
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void ipq_configure_gpio(gpio_func_data_t *gpio, unsigned count);
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#endif
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#endif
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@ -43,6 +43,8 @@
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*/
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*/
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#define readl_i(a) read32((const void *)(a))
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#define readl_i(a) read32((const void *)(a))
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#define writel_i(v,a) write32(v,(void *)a)
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#define writel_i(v,a) write32(v,(void *)a)
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#include <arch/io.h>
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#include <cdp.h>
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#define MSM_CLK_CTL_BASE 0x00900000
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#define MSM_CLK_CTL_BASE 0x00900000
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@ -50,7 +52,7 @@
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#define MSM_GPT_BASE (MSM_TMR_BASE + 0x04)
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#define MSM_GPT_BASE (MSM_TMR_BASE + 0x04)
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#define MSM_DGT_BASE (MSM_TMR_BASE + 0x24)
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#define MSM_DGT_BASE (MSM_TMR_BASE + 0x24)
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#define GPT_REG(off) (MSM_GPT_BASE + (off))
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#define GPT_REG(off) (((uint8_t *)(MSM_GPT_BASE)) + (off))
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#define DGT_REG(off) (MSM_DGT_BASE + (off))
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#define DGT_REG(off) (MSM_DGT_BASE + (off))
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#define APCS_WDT0_EN (MSM_TMR_BASE + 0x0040)
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#define APCS_WDT0_EN (MSM_TMR_BASE + 0x0040)
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@ -31,14 +31,10 @@
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* SUCH DAMAGE.
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* SUCH DAMAGE.
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*/
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*/
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#include <asm/arch-ipq806x/iomap.h>
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#include <delay.h>
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#include <asm/io.h>
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#include <iomap.h>
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#include <common.h>
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#include <ipq_timer.h>
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#include <asm/types.h>
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#include <timer.h>
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#include <asm/arch-ipq806x/timer.h>
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static ulong timestamp;
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static ulong lastinc;
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#define GPT_FREQ_KHZ 32
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#define GPT_FREQ_KHZ 32
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#define GPT_FREQ (GPT_FREQ_KHZ * 1000) /* 32 KHz */
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#define GPT_FREQ (GPT_FREQ_KHZ * 1000) /* 32 KHz */
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@ -46,36 +42,24 @@ static ulong lastinc;
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/**
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/**
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* timer_init - initialize timer
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* timer_init - initialize timer
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*/
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*/
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int timer_init(void)
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void init_timer(void)
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{
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{
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writel(0, GPT_ENABLE);
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writel(0, GPT_ENABLE);
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writel(GPT_ENABLE_EN, GPT_ENABLE);
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writel(GPT_ENABLE_EN, GPT_ENABLE);
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return 0;
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}
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}
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/**
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/**
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* get_timer - returns time lapsed
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* udelay - generates micro second delay.
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* @base: base/start time
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*
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* Returns time lapsed, since the specified base time value.
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*/
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ulong get_timer(ulong base)
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{
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return get_timer_masked() - base;
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}
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/**
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* __udelay - generates micro second delay.
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* @usec: delay duration in microseconds
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* @usec: delay duration in microseconds
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*
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*
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* With 32KHz clock, minimum possible delay is 31.25 Micro seconds and
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* With 32KHz clock, minimum possible delay is 31.25 Micro seconds and
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* its multiples. In Rumi GPT clock is 32 KHz
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* its multiples. In Rumi GPT clock is 32 KHz
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*/
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*/
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void __udelay(unsigned long usec)
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void udelay(unsigned usec)
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{
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{
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unsigned int val;
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unsigned val;
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ulong now, last;
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unsigned now, last;
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ulong runcount;
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unsigned runcount;
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usec = (usec + GPT_FREQ_KHZ - 1) / GPT_FREQ_KHZ;
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usec = (usec + GPT_FREQ_KHZ - 1) / GPT_FREQ_KHZ;
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last = readl(GPT_COUNT_VAL);
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last = readl(GPT_COUNT_VAL);
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@ -92,6 +76,15 @@ void __udelay(unsigned long usec)
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} while (runcount < val);
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} while (runcount < val);
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}
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}
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#if 0
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/*
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* TODO(vbendeb) clean it up later.
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* Compile out the below code but leave it for now in case it will become
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* necessary later in order to make the platform fully functional.
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*/
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static unsigned long timestamp;
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static unsigned long lastinc;
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inline ulong gpt_to_sys_freq(unsigned int gpt)
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inline ulong gpt_to_sys_freq(unsigned int gpt)
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{
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{
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{
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{
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return GPT_FREQ;
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return GPT_FREQ;
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}
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}
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#endif
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