soc/mediatek: Fix I2C failures by adjusting AC timing and bus speed
1. The original algorithm for I2C speed cannot always make the timing meet I2C specification so a new algorithm is introduced to calculate the timing parameters more correctly. 2. Some I2C buses should be initialized in a different speed while the original implementation was fixed at fast mode (400Khz). So the mtk_i2c_bus_init is now also taking an extra speed parameter. There is an equivalent change in kernel side: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/i2c/busses/i2c-mt65xx.c?h=v5.15-rc3&id=be5ce0e97cc7a5c0d2da45d617b7bc567c3d3fa1 BUG=b:189899864 TEST=Test on Tomato, boot pass and timing pass at 100/300/400/500/800/1000Khz. Signed-off-by: Daolong Zhu <jg_daolongzhu@mediatek.corp-partner.google.com> Change-Id: Id25b7bb3a76908a7943b940eb5bee799e80626a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58053 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Daolong Zhu
Felix Held
parent
38abbdab71
commit
f4b71734b2
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@ -43,7 +43,7 @@ static void usb3_hub_reset(void)
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void bootblock_mainboard_init(void)
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{
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mtk_i2c_bus_init(CONFIG_DRIVER_TPM_I2C_BUS);
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mtk_i2c_bus_init(CONFIG_DRIVER_TPM_I2C_BUS, I2C_SPEED_FAST);
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mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0);
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nor_set_gpio_pinmux();
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setup_chromeos_gpios();
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@ -131,7 +131,7 @@ static void configure_sdcard(void)
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MSDC1_GPIO_MODE1_2, MSDC1_GPIO_MODE1_VALUE,
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MSDC1_GPIO_MODE1_3, MSDC1_GPIO_MODE1_VALUE);
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mtk_i2c_bus_init(I2C7);
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mtk_i2c_bus_init(I2C7, I2C_SPEED_FAST);
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if (CONFIG(BOARD_GOOGLE_CHERRY))
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mt6360_init(I2C7);
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@ -205,7 +205,7 @@ static void mainboard_init(struct device *dev)
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/* for audio usage */
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if (CONFIG(CHERRY_USE_RT1011))
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mtk_i2c_bus_init(I2C2);
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mtk_i2c_bus_init(I2C2, I2C_SPEED_FAST);
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if (dpm_init())
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printk(BIOS_ERR, "dpm init failed, DVFS may not work\n");
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@ -28,7 +28,7 @@ void platform_romstage_main(void)
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mt6359p_init();
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mt6315_init();
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raise_little_cpu_freq();
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mtk_i2c_bus_init(I2C7);
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mtk_i2c_bus_init(I2C7, I2C_SPEED_FAST);
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if (CONFIG(BOARD_GOOGLE_CHERRY))
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mt6360_init(I2C7);
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clk_buf_init();
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@ -10,6 +10,39 @@
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#include <soc/i2c.h>
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#include <device/i2c_simple.h>
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const struct i2c_spec_values standard_mode_spec = {
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.min_low_ns = 4700 + I2C_STANDARD_MODE_BUFFER,
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.min_su_sta_ns = 4700 + I2C_STANDARD_MODE_BUFFER,
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.max_hd_dat_ns = 3450 - I2C_STANDARD_MODE_BUFFER,
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.min_su_dat_ns = 250 + I2C_STANDARD_MODE_BUFFER,
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};
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const struct i2c_spec_values fast_mode_spec = {
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.min_low_ns = 1300 + I2C_FAST_MODE_BUFFER,
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.min_su_sta_ns = 600 + I2C_FAST_MODE_BUFFER,
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.max_hd_dat_ns = 900 - I2C_FAST_MODE_BUFFER,
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.min_su_dat_ns = 100 + I2C_FAST_MODE_BUFFER,
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};
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const struct i2c_spec_values fast_mode_plus_spec = {
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.min_low_ns = 500 + I2C_FAST_MODE_PLUS_BUFFER,
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.min_su_sta_ns = 260 + I2C_FAST_MODE_PLUS_BUFFER,
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.max_hd_dat_ns = 400 - I2C_FAST_MODE_PLUS_BUFFER,
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.min_su_dat_ns = 50 + I2C_FAST_MODE_PLUS_BUFFER,
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};
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__weak void mtk_i2c_dump_more_info(struct mt_i2c_regs *regs) { /* do nothing */ }
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const struct i2c_spec_values *mtk_i2c_get_spec(uint32_t speed)
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{
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if (speed <= I2C_SPEED_STANDARD)
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return &standard_mode_spec;
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else if (speed <= I2C_SPEED_FAST)
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return &fast_mode_spec;
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else
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return &fast_mode_plus_spec;
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}
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static inline void i2c_hw_reset(uint8_t bus)
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{
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struct mt_i2c_regs *regs;
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@ -42,7 +75,7 @@ static inline void i2c_hw_reset(uint8_t bus)
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static inline void mtk_i2c_dump_info(struct mt_i2c_regs *regs)
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{
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printk(BIOS_ERR, "I2C register:\nSLAVE_ADDR %x\nINTR_MASK %x\n"
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printk(BIOS_DEBUG, "I2C register:\nSLAVE_ADDR %x\nINTR_MASK %x\n"
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"INTR_STAT %x\nCONTROL %x\nTRANSFER_LEN %x\nTRANSAC_LEN %x\n"
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"DELAY_LEN %x\nTIMING %x\nSTART %x\nFIFO_STAT %x\nIO_CONFIG %x\n"
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"HS %x\nDEBUGSTAT %x\nEXT_CONF %x\n",
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@ -60,6 +93,8 @@ static inline void mtk_i2c_dump_info(struct mt_i2c_regs *regs)
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read32(®s->hs),
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read32(®s->debug_stat),
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read32(®s->ext_conf));
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mtk_i2c_dump_more_info(regs);
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}
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static uint32_t mtk_i2c_transfer(uint8_t bus, struct i2c_msg *seg,
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@ -3,6 +3,8 @@
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#ifndef MTK_COMMON_I2C_H
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#define MTK_COMMON_I2C_H
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#include <device/i2c.h>
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/* I2C DMA Registers */
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struct mt_i2c_dma_regs {
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uint32_t dma_int_flag;
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@ -84,7 +86,6 @@ enum {
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};
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/* I2C Status Code */
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enum {
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I2C_OK = 0x0000,
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I2C_SET_SPEED_FAIL_OVER_SPEED = 0xA001,
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@ -95,11 +96,51 @@ enum {
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I2C_TRANSFER_INVALID_ARGUMENT = 0xA006
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};
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struct mtk_i2c_ac_timing {
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u16 htiming;
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u16 ltiming;
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u16 hs;
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u16 ext;
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u16 inter_clk_div;
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u16 scl_hl_ratio;
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u16 hs_scl_hl_ratio;
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u16 sta_stop;
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u16 hs_sta_stop;
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u16 sda_timing;
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};
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struct mtk_i2c {
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struct mt_i2c_regs *i2c_regs;
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struct mt_i2c_dma_regs *i2c_dma_regs;
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struct mtk_i2c_ac_timing ac_timing;
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uint32_t mt_i2c_flag;
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};
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#define I2C_TIME_CLR_VALUE 0x0000
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#define MAX_SAMPLE_CNT_DIV 8
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#define MAX_STEP_CNT_DIV 64
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#define MAX_HS_STEP_CNT_DIV 8
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#define I2C_TIME_DEFAULT_VALUE 0x0083
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#define I2C_STANDARD_MODE_BUFFER (1000 / 3)
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#define I2C_FAST_MODE_BUFFER (300 / 3)
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#define I2C_FAST_MODE_PLUS_BUFFER (20 / 3)
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/*
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* struct i2c_spec_values:
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* @min_low_ns: min LOW period of the SCL clock
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* @min_su_sta_ns: min set-up time for a repeated START condition
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* @max_hd_dat_ns: max data hold time
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* @min_su_dat_ns: min data set-up time
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*/
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struct i2c_spec_values {
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uint32_t min_low_ns;
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uint32_t min_su_sta_ns;
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uint32_t max_hd_dat_ns;
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uint32_t min_su_dat_ns;
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};
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extern struct mtk_i2c mtk_i2c_bus_controller[];
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const struct i2c_spec_values *mtk_i2c_get_spec(uint32_t speed);
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void mtk_i2c_dump_more_info(struct mt_i2c_regs *regs);
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#endif
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@ -1,16 +1,15 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <assert.h>
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#include <console/console.h>
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#include <device/mmio.h>
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#include <device/i2c_simple.h>
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#include <soc/pll.h>
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#include <soc/i2c.h>
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#include <soc/gpio.h>
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#include <timer.h>
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#define I2C_CLK_HZ (UNIVPLL_HZ / 20)
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#define I2C_FULL_DUTY 100
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#define I2C_HALF_DUTY 50
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#define I2C_ADJUSTED_DUTY 50
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#define I2C_FS_START_CON 0x0
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struct mtk_i2c mtk_i2c_bus_controller[] = {
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[0] = {
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@ -112,57 +111,247 @@ static void mtk_i2c_set_gpio_pinmux(uint8_t bus)
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}
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}
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static void mtk_i2c_speed_init(uint8_t bus)
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static int mtk_i2c_max_step_cnt(uint32_t target_speed)
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{
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uint8_t step_div;
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const uint8_t clock_div = 5;
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const uint8_t sample_div = 1;
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uint32_t i2c_freq;
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uint32_t tar_speed = 400;
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uint32_t tar_speed_high;
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uint32_t tar_speed_low;
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if (target_speed > I2C_SPEED_FAST_PLUS)
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return MAX_HS_STEP_CNT_DIV;
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else
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return MAX_STEP_CNT_DIV;
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}
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assert(bus < I2C_BUS_NUMBER);
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/*
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* Check and calculate i2c ac-timing.
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*
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* Hardware design:
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* sample_ns = (1000000000 * (sample_cnt + 1)) / clk_src
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* xxx_cnt_div = spec->min_xxx_ns / sample_ns
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*
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* The calculation of sample_ns is rounded down;
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* otherwise xxx_cnt_div would be greater than the smallest spec.
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* The sda_timing is chosen as the middle value between
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* the largest and smallest.
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*/
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static int mtk_i2c_check_ac_timing(uint8_t bus, uint32_t clk_src,
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uint32_t check_speed,
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uint32_t step_cnt,
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uint32_t sample_cnt)
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{
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const struct i2c_spec_values *spec;
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uint32_t su_sta_cnt, low_cnt, high_cnt, max_step_cnt;
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uint32_t sda_max, sda_min, clk_ns, max_sta_cnt = 0x100;
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uint32_t sample_ns = ((uint64_t)NSECS_PER_SEC * (sample_cnt + 1)) / clk_src;
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struct mtk_i2c_ac_timing *ac_timing;
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/* Adjust ratio of high/low level */
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tar_speed_high = tar_speed * I2C_HALF_DUTY / I2C_ADJUSTED_DUTY;
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spec = mtk_i2c_get_spec(check_speed);
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/* Calculate i2c frequency */
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step_div = DIV_ROUND_UP(I2C_CLK_HZ,
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(tar_speed_high * KHz * sample_div * 2) * clock_div);
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i2c_freq = I2C_CLK_HZ / (step_div * sample_div * 2 * clock_div);
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assert(sample_div < 8 && step_div < 64 &&
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i2c_freq <= tar_speed_high * KHz &&
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i2c_freq >= (tar_speed_high - 20) * KHz);
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clk_ns = NSECS_PER_SEC / clk_src;
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su_sta_cnt = DIV_ROUND_UP(spec->min_su_sta_ns, clk_ns);
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if (su_sta_cnt > max_sta_cnt)
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return -1;
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low_cnt = DIV_ROUND_UP(spec->min_low_ns, sample_ns);
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max_step_cnt = mtk_i2c_max_step_cnt(check_speed);
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if (2 * step_cnt > low_cnt && low_cnt < max_step_cnt) {
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if (low_cnt > step_cnt) {
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high_cnt = 2 * step_cnt - low_cnt;
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} else {
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high_cnt = step_cnt;
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low_cnt = step_cnt;
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}
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} else {
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return -2;
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}
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sda_max = spec->max_hd_dat_ns / sample_ns;
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if (sda_max > low_cnt)
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sda_max = 0;
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sda_min = DIV_ROUND_UP(spec->min_su_dat_ns, sample_ns);
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if (sda_min < low_cnt)
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sda_min = 0;
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if (sda_min > sda_max)
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return -3;
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ac_timing = &mtk_i2c_bus_controller[bus].ac_timing;
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if (check_speed > I2C_SPEED_FAST_PLUS) {
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ac_timing->hs = I2C_TIME_DEFAULT_VALUE | (sample_cnt << 12) | (high_cnt << 8);
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ac_timing->ltiming &= ~GENMASK(15, 9);
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ac_timing->ltiming |= (sample_cnt << 12) | (low_cnt << 9);
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ac_timing->ext &= ~GENMASK(7, 1);
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ac_timing->ext |= (su_sta_cnt << 1) | (1 << 0);
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} else {
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ac_timing->htiming = (sample_cnt << 8) | (high_cnt);
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ac_timing->ltiming = (sample_cnt << 6) | (low_cnt);
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ac_timing->ext = (su_sta_cnt << 8) | (1 << 0);
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}
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return 0;
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}
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/*
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* Calculate i2c port speed.
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*
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* Hardware design:
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* i2c_bus_freq = parent_clk / (clock_div * 2 * sample_cnt * step_cnt)
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* clock_div: fixed in hardware, but may be various in different SoCs
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*
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* To calculate sample_cnt and step_cnt, we pick the highest bus frequency
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* that is still no larger than i2c->speed_hz.
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*/
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static int mtk_i2c_calculate_speed(uint8_t bus, uint32_t clk_src,
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uint32_t target_speed,
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uint32_t *timing_step_cnt,
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uint32_t *timing_sample_cnt)
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{
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uint32_t step_cnt;
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uint32_t sample_cnt;
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uint32_t max_step_cnt;
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uint32_t base_sample_cnt = MAX_SAMPLE_CNT_DIV;
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uint32_t base_step_cnt;
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uint32_t opt_div;
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uint32_t best_mul;
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uint32_t cnt_mul;
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uint32_t clk_div = mtk_i2c_bus_controller[bus].ac_timing.inter_clk_div;
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int32_t clock_div_constraint = 0;
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int success = 0;
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if (target_speed > I2C_SPEED_HIGH)
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target_speed = I2C_SPEED_HIGH;
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max_step_cnt = mtk_i2c_max_step_cnt(target_speed);
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base_step_cnt = max_step_cnt;
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/* Find the best combination */
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opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed);
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best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt;
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/* Search for the best pair (sample_cnt, step_cnt) with
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* 0 < sample_cnt < MAX_SAMPLE_CNT_DIV
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* 0 < step_cnt < max_step_cnt
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* sample_cnt * step_cnt >= opt_div
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* optimizing for sample_cnt * step_cnt being minimal
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*/
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for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) {
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if (sample_cnt == 1) {
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if (clk_div != 0)
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clock_div_constraint = 1;
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else
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clock_div_constraint = 0;
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} else {
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if (clk_div > 1)
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clock_div_constraint = 1;
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else if (clk_div == 0)
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clock_div_constraint = -1;
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else
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clock_div_constraint = 0;
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}
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step_cnt = DIV_ROUND_UP(opt_div + clock_div_constraint, sample_cnt);
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if (step_cnt > max_step_cnt)
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continue;
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cnt_mul = step_cnt * sample_cnt;
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if (cnt_mul >= best_mul)
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continue;
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if (mtk_i2c_check_ac_timing(bus, clk_src,
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target_speed, step_cnt - 1,
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sample_cnt - 1))
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continue;
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success = 1;
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best_mul = cnt_mul;
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base_sample_cnt = sample_cnt;
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base_step_cnt = step_cnt;
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if (best_mul == opt_div + clock_div_constraint)
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break;
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}
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if (!success)
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return -1;
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sample_cnt = base_sample_cnt;
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step_cnt = base_step_cnt;
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if (clk_src / (2 * (sample_cnt * step_cnt - clock_div_constraint)) >
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target_speed)
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return -1;
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*timing_step_cnt = step_cnt - 1;
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*timing_sample_cnt = sample_cnt - 1;
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return 0;
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}
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static void mtk_i2c_speed_init(uint8_t bus, uint32_t speed)
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{
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uint32_t max_clk_div = MAX_CLOCK_DIV;
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uint32_t clk_src, clk_div, step_cnt, sample_cnt;
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uint32_t l_step_cnt, l_sample_cnt;
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uint32_t timing_reg_value, ltiming_reg_value;
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struct mtk_i2c *bus_ctrl;
|
||||
|
||||
if (bus >= I2C_BUS_NUMBER) {
|
||||
printk(BIOS_ERR, "%s, error bus num:%d\n", __func__, bus);
|
||||
return;
|
||||
}
|
||||
|
||||
bus_ctrl = &mtk_i2c_bus_controller[bus];
|
||||
|
||||
for (clk_div = 1; clk_div <= max_clk_div; clk_div++) {
|
||||
clk_src = I2C_CLK_HZ / clk_div;
|
||||
bus_ctrl->ac_timing.inter_clk_div = clk_div - 1;
|
||||
|
||||
if (speed > I2C_SPEED_FAST_PLUS) {
|
||||
/* Set master code speed register */
|
||||
if (mtk_i2c_calculate_speed(bus, clk_src, I2C_SPEED_FAST,
|
||||
&l_step_cnt, &l_sample_cnt))
|
||||
continue;
|
||||
|
||||
timing_reg_value = (l_sample_cnt << 8) | l_step_cnt;
|
||||
|
||||
/* Set the high speed mode register */
|
||||
if (mtk_i2c_calculate_speed(bus, clk_src, speed,
|
||||
&step_cnt, &sample_cnt))
|
||||
continue;
|
||||
|
||||
ltiming_reg_value = (l_sample_cnt << 6) | l_step_cnt |
|
||||
(sample_cnt << 12) | (step_cnt << 9);
|
||||
bus_ctrl->ac_timing.inter_clk_div = (clk_div - 1) << 8 | (clk_div - 1);
|
||||
} else {
|
||||
if (mtk_i2c_calculate_speed(bus, clk_src, speed,
|
||||
&l_step_cnt, &l_sample_cnt))
|
||||
continue;
|
||||
|
||||
timing_reg_value = (l_sample_cnt << 8) | l_step_cnt;
|
||||
|
||||
/* Disable the high speed transaction */
|
||||
bus_ctrl->ac_timing.hs = I2C_TIME_CLR_VALUE;
|
||||
|
||||
ltiming_reg_value = (l_sample_cnt << 6) | l_step_cnt;
|
||||
}
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
if (clk_div > max_clk_div) {
|
||||
printk(BIOS_ERR, "%s, cannot support %d hz on i2c-%d\n", __func__, speed, bus);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Init i2c bus timing register */
|
||||
write32(&mtk_i2c_bus_controller[bus].i2c_regs->timing,
|
||||
(sample_div - 1) << 8 | (step_div - 1));
|
||||
|
||||
/* Adjust ratio of high/low level */
|
||||
tar_speed_low = tar_speed * I2C_HALF_DUTY /
|
||||
(I2C_FULL_DUTY - I2C_ADJUSTED_DUTY);
|
||||
|
||||
/* Calculate i2c frequency */
|
||||
step_div = DIV_ROUND_UP(I2C_CLK_HZ,
|
||||
(tar_speed_low * KHz * sample_div * 2) * clock_div);
|
||||
i2c_freq = I2C_CLK_HZ / (step_div * sample_div * 2 * clock_div);
|
||||
assert(sample_div < 8 && step_div < 64 &&
|
||||
i2c_freq <= tar_speed_low * KHz &&
|
||||
i2c_freq >= (tar_speed_low - 20) * KHz);
|
||||
write32(&mtk_i2c_bus_controller[bus].i2c_regs->ltiming,
|
||||
(sample_div - 1) << 6 | (step_div - 1));
|
||||
|
||||
/* Init i2c bus clock_div register */
|
||||
write32(&mtk_i2c_bus_controller[bus].i2c_regs->clock_div,
|
||||
clock_div - 1);
|
||||
|
||||
/* Adjust tSU,STA/tHD,STA/tSU,STO */
|
||||
write32(&mtk_i2c_bus_controller[bus].i2c_regs->ext_conf, I2C_FS_START_CON);
|
||||
write32(&bus_ctrl->i2c_regs->clock_div, bus_ctrl->ac_timing.inter_clk_div);
|
||||
write32(&bus_ctrl->i2c_regs->timing, bus_ctrl->ac_timing.htiming);
|
||||
write32(&bus_ctrl->i2c_regs->ltiming, bus_ctrl->ac_timing.ltiming);
|
||||
write32(&bus_ctrl->i2c_regs->hs, bus_ctrl->ac_timing.hs);
|
||||
write32(&bus_ctrl->i2c_regs->ext_conf, bus_ctrl->ac_timing.ext);
|
||||
}
|
||||
|
||||
void mtk_i2c_bus_init(uint8_t bus)
|
||||
void mtk_i2c_bus_init(uint8_t bus, uint32_t speed)
|
||||
{
|
||||
mtk_i2c_speed_init(bus);
|
||||
mtk_i2c_speed_init(bus, speed);
|
||||
mtk_i2c_set_gpio_pinmux(bus);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -22,7 +22,8 @@ struct mt_i2c_regs {
|
|||
uint32_t hs;
|
||||
uint32_t io_config;
|
||||
uint32_t fifo_addr_clr;
|
||||
uint32_t reserved0[2];
|
||||
uint32_t data_timing;
|
||||
uint32_t reserved0;
|
||||
uint32_t transfer_aux_len;
|
||||
uint32_t clock_div;
|
||||
uint32_t time_out;
|
||||
|
|
@ -51,8 +52,9 @@ enum {
|
|||
I2C7,
|
||||
};
|
||||
|
||||
#define MAX_CLOCK_DIV 32
|
||||
check_member(mt_i2c_regs, multi_dma, 0xf8c);
|
||||
|
||||
void mtk_i2c_bus_init(uint8_t bus);
|
||||
void mtk_i2c_bus_init(uint8_t bus, uint32_t speed);
|
||||
|
||||
#endif /* SOC_MEDIATEK_MT8195_I2C_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue