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amd/dinar & torpedo: Remove trailing whitespace 

Change-Id: I4ac14c4f511eb6d56480e5167ce98b861cbed775
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: http://review.coreboot.org/6322
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
Elyes HAOUAS 2014-07-22 23:45:01 +02:00 committed by Patrick Georgi
parent 1631c880eb
commit f4d1d3b986
3 changed files with 47 additions and 47 deletions
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72
src/mainboard/amd/dinar/agesawrapper.h
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@ -25,44 +25,44 @@
#include "AGESA.h" #include "AGESA.h"
/* Define AMD Ontario APPU SSID/SVID */ /* Define AMD Ontario APPU SSID/SVID */
#define AMD_APU_SVID 0x1022 #define AMD_APU_SVID 0x1022
#define AMD_APU_SSID 0x1234 #define AMD_APU_SSID 0x1234
#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS #define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
#define MMIO_NP_BIT BIT7 #define MMIO_NP_BIT BIT7
/* Hudson-2 ACPI PmIO Space Define */ /* Hudson-2 ACPI PmIO Space Define */
#define SB_ACPI_BASE_ADDRESS 0x0400 #define SB_ACPI_BASE_ADDRESS 0x0400
#define ACPI_MMIO_BASE 0xFED80000 #define ACPI_MMIO_BASE 0xFED80000
#define SB_CFG_BASE 0x000 // DWORD #define SB_CFG_BASE 0x000 // DWORD
#define GPIO_BASE 0x100 // BYTE #define GPIO_BASE 0x100 // BYTE
#define SMI_BASE 0x200 // DWORD #define SMI_BASE 0x200 // DWORD
#define PMIO_BASE 0x300 // DWORD #define PMIO_BASE 0x300 // DWORD
#define PMIO2_BASE 0x400 // BYTE #define PMIO2_BASE 0x400 // BYTE
#define BIOS_RAM_BASE 0x500 // BYTE #define BIOS_RAM_BASE 0x500 // BYTE
#define CMOS_RAM_BASE 0x600 // BYTE #define CMOS_RAM_BASE 0x600 // BYTE
#define CMOS_BASE 0x700 // BYTE #define CMOS_BASE 0x700 // BYTE
#define ASF_BASE 0x900 // DWORD #define ASF_BASE 0x900 // DWORD
#define SMBUS_BASE 0xA00 // DWORD #define SMBUS_BASE 0xA00 // DWORD
#define WATCHDOG_BASE 0xB00 // ?? #define WATCHDOG_BASE 0xB00 // ??
#define HPET_BASE 0xC00 // DWORD #define HPET_BASE 0xC00 // DWORD
#define IOMUX_BASE 0xD00 // BYTE #define IOMUX_BASE 0xD00 // BYTE
#define MISC_BASE 0xE00 #define MISC_BASE 0xE00
#define SERIAL_DEBUG_BASE 0x1000 #define SERIAL_DEBUG_BASE 0x1000
#define GFX_DAC_BASE 0x1400 #define GFX_DAC_BASE 0x1400
#define CEC_BASE 0x1800 #define CEC_BASE 0x1800
#define XHCI_BASE 0x1C00 #define XHCI_BASE 0x1C00
#define ACPI_SMI_DATA_PORT 0xB1 #define ACPI_SMI_DATA_PORT 0xB1
#define R_SB_ACPI_PM1_STATUS 0x00 #define R_SB_ACPI_PM1_STATUS 0x00
#define R_SB_ACPI_PM1_ENABLE 0x02 #define R_SB_ACPI_PM1_ENABLE 0x02
#define R_SB_ACPI_PM_CONTROL 0x04 #define R_SB_ACPI_PM_CONTROL 0x04
#define R_SB_ACPI_EVENT_STATUS 0x20 #define R_SB_ACPI_EVENT_STATUS 0x20
#define R_SB_ACPI_EVENT_ENABLE 0x24 #define R_SB_ACPI_EVENT_ENABLE 0x24
#define B_PWR_BTN_STATUS BIT8 #define B_PWR_BTN_STATUS BIT8
#define B_WAKEUP_STATUS BIT15 #define B_WAKEUP_STATUS BIT15
#define B_SCI_EN BIT0 #define B_SCI_EN BIT0
#define SB_PM_INDEX_PORT 0xCD6 #define SB_PM_INDEX_PORT 0xCD6
#define SB_PM_DATA_PORT 0xCD7 #define SB_PM_DATA_PORT 0xCD7
#define SB_PMIOA_REG24 0x24 // AcpiMmioEn #define SB_PMIOA_REG24 0x24 // AcpiMmioEn
#define MmioAddress( BaseAddr, Register ) \ #define MmioAddress( BaseAddr, Register ) \
( (UINTN)BaseAddr + \ ( (UINTN)BaseAddr + \
(UINTN)(Register) \ (UINTN)(Register) \

18
src/mainboard/amd/dinar/buildOpts.c
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@ -42,15 +42,15 @@
* coreboot enable -Wundef option, so we should make sure we have all contanstand defined * coreboot enable -Wundef option, so we should make sure we have all contanstand defined
*/ */
/* MEMORY_BUS_SPEED */ /* MEMORY_BUS_SPEED */
#define DDR400_FREQUENCY 200 ///< DDR 400 #define DDR400_FREQUENCY 200 ///< DDR 400
#define DDR533_FREQUENCY 266 ///< DDR 533 #define DDR533_FREQUENCY 266 ///< DDR 533
#define DDR667_FREQUENCY 333 ///< DDR 667 #define DDR667_FREQUENCY 333 ///< DDR 667
#define DDR800_FREQUENCY 400 ///< DDR 800 #define DDR800_FREQUENCY 400 ///< DDR 800
#define DDR1066_FREQUENCY 533 ///< DDR 1066 #define DDR1066_FREQUENCY 533 ///< DDR 1066
#define DDR1333_FREQUENCY 667 ///< DDR 1333 #define DDR1333_FREQUENCY 667 ///< DDR 1333
#define DDR1600_FREQUENCY 800 ///< DDR 1600 #define DDR1600_FREQUENCY 800 ///< DDR 1600
#define DDR1866_FREQUENCY 933 ///< DDR 1866 #define DDR1866_FREQUENCY 933 ///< DDR 1866
#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency #define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency
/* QUANDRANK_TYPE */ /* QUANDRANK_TYPE */
#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM #define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM

4
src/mainboard/amd/dinar/platform_cfg.h
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@ -31,13 +31,13 @@
* Enable check for PCIe endpoint to be ready for PCI enumeration. * Enable check for PCIe endpoint to be ready for PCI enumeration.
* *
*/ */
//#define EPREADY_WORKAROUND_DISABLED //#define EPREADY_WORKAROUND_DISABLED
/** /**
* Enable IOMMU support. Initialize IOMMU subsystem, generate IVRS ACPI table. * Enable IOMMU support. Initialize IOMMU subsystem, generate IVRS ACPI table.
* *
*/ */
#define IOMMU_SUPPORT_DISABLE //TODO: enable it #define IOMMU_SUPPORT_DISABLE //TODO: enable it
/** /**
* Disable server PCIe hotplug support. * Disable server PCIe hotplug support.