GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

3rdparty: Move to blobs 

To move 3rdparty to 3rdparty/blobs (ie. below itself
from git's broken perspective), we need to work around
it - since some git implementations don't like the direct
approach.

Change-Id: I1fc84bbb37e7c8c91ab14703d609a739b5ca073c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10108
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Patrick Georgi 2015-05-05 22:24:10 +02:00 committed by Patrick Georgi
parent b9cd5ece14
commit f4f028790a
51 changed files with 73 additions and 73 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
.gitmodules vendored
View File

@ -1,5 +1,5 @@
[submodule "3rdparty"]
path = 3rdparty
path = blobs
url = ../blobs.git
update = none
ignore = dirty

4
Makefile.inc
View File

@ -131,9 +131,9 @@ endif
# try to fetch non-optional submodules if the source is under git
forgetthis:=$(if $(GIT),$(shell git submodule update --init))
ifeq ($(CONFIG_USE_BLOBS),y)
# this is necessary because 3rdparty is update=none, and so is ignored
# this is necessary because blobs is update=none, and so is ignored
# unless explicitly requested and enabled through --checkout
forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty))
forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout blobs))
endif
ramstage-c-deps:=$$(OPTION_TABLE_H)

0
3rdparty → blobs
View File

2
src/cpu/amd/geode_gx2/Makefile.inc
View File

@ -11,4 +11,4 @@ cpu_incs += $(src)/cpu/amd/geode_gx2/cache_as_ram.inc
cbfs-files-$(CONFIG_GEODE_VSA_FILE) += vsa
vsa-file = $(call strip_quotes,$(CONFIG_VSA_FILENAME)):vsa
vsa-type = stage
vsa-required = VSA binary (binary and MASM source code available in coreboot/3rdparty repository)
vsa-required = VSA binary (binary and MASM source code available in coreboot/blobs repository)

2
src/cpu/amd/geode_lx/Kconfig
View File

@ -37,7 +37,7 @@ config GEODE_VSA_FILE
config VSA_FILENAME
string "AMD Geode LX VSA path and filename"
depends on GEODE_VSA_FILE
default "3rdparty/cpu/amd/geode_lx/gpl_vsa_lx_102.bin"
default "blobs/cpu/amd/geode_lx/gpl_vsa_lx_102.bin"
help
The path and filename of the file to use as VSA.

2
src/cpu/amd/geode_lx/Makefile.inc
View File

@ -11,4 +11,4 @@ cpu_incs += $(src)/cpu/amd/geode_lx/cache_as_ram.inc
cbfs-files-$(CONFIG_GEODE_VSA_FILE) += vsa
vsa-file = $(call strip_quotes,$(CONFIG_VSA_FILENAME)):vsa
vsa-type = stage
vsa-required = VSA binary (binary and MASM source code available in coreboot/3rdparty repository)
vsa-required = VSA binary (binary and MASM source code available in coreboot/blobs repository)

4
src/cpu/intel/haswell/microcode_blob.c
View File

@ -23,8 +23,8 @@ unsigned microcode[] = {
* a very good reason why we only use one at a time?
*/
#if CONFIG_INTEL_LYNXPOINT_LP
#include "../../../../3rdparty/cpu/intel/model_4065x/microcode.h"
#include "../../../../blobs/cpu/intel/model_4065x/microcode.h"
#else
#include "../../../../3rdparty/cpu/intel/model_306cx/microcode.h"
#include "../../../../blobs/cpu/intel/model_306cx/microcode.h"
#endif
};

2
src/cpu/intel/model_1067x/microcode_blob.c
View File

@ -1,3 +1,3 @@
unsigned microcode_updates_1067ax[] = {
#include "../../../../3rdparty/cpu/intel/model_1067x/microcode.h"
#include "../../../../blobs/cpu/intel/model_1067x/microcode.h"
};

2
src/cpu/intel/model_106cx/microcode_blob.c
View File

@ -1,3 +1,3 @@
unsigned microcode_updates_106cx[] = {
#include "../../../../3rdparty/cpu/intel/model_106cx/microcode.h"
#include "../../../../blobs/cpu/intel/model_106cx/microcode.h"
};

2
src/cpu/intel/model_2065x/microcode_blob.c
View File

@ -18,5 +18,5 @@
*/
unsigned microcode[] = {
#include "../../../../3rdparty/cpu/intel/model_2065x/microcode.h"
#include "../../../../blobs/cpu/intel/model_2065x/microcode.h"
};

2
src/cpu/intel/model_206ax/microcode_blob.c
View File

@ -18,5 +18,5 @@
*/
unsigned microcode[] = {
#include "../../../../3rdparty/cpu/intel/model_206ax/microcode.h"
#include "../../../../blobs/cpu/intel/model_206ax/microcode.h"
};

2
src/cpu/intel/model_65x/microcode_blob.c
View File

@ -1,3 +1,3 @@
unsigned microcode_updates_65x[] = {
#include "../../../../3rdparty/cpu/intel/model_65x/microcode.h"
#include "../../../../blobs/cpu/intel/model_65x/microcode.h"
};

2
src/cpu/intel/model_67x/microcode_blob.c
View File

@ -1,3 +1,3 @@
unsigned microcode_updates_67x[] = {
#include "../../../../3rdparty/cpu/intel/model_67x/microcode.h"
#include "../../../../blobs/cpu/intel/model_67x/microcode.h"
};

2
src/cpu/intel/model_68x/microcode_blob.c
View File

@ -1,3 +1,3 @@
unsigned microcode_updates_68x[] = {
#include "../../../../3rdparty/cpu/intel/model_68x/microcode.h"
#include "../../../../blobs/cpu/intel/model_68x/microcode.h"
};

2
src/cpu/intel/model_69x/microcode_blob.c
View File

@ -1,3 +1,3 @@
unsigned microcode_updates_69x[] = {
#include "../../../../3rdparty/cpu/intel/model_69x/microcode.h"
#include "../../../../blobs/cpu/intel/model_69x/microcode.h"
};

2
src/cpu/intel/model_6bx/microcode_blob.c
View File

@ -1,3 +1,3 @@
unsigned microcode_updates_6bx[] = {
#include "../../../../3rdparty/cpu/intel/model_6bx/microcode.h"
#include "../../../../blobs/cpu/intel/model_6bx/microcode.h"
};

2
src/cpu/intel/model_6dx/microcode_blob.c
View File

@ -1,3 +1,3 @@
unsigned microcode_updates_6dx[] = {
#include "../../../../3rdparty/cpu/intel/model_6dx/microcode.h"
#include "../../../../blobs/cpu/intel/model_6dx/microcode.h"
};

2
src/cpu/intel/model_6ex/microcode_blob.c
View File

@ -1,3 +1,3 @@
unsigned microcode_updates_6ex[] = {
#include "../../../../3rdparty/cpu/intel/model_6ex/microcode.h"
#include "../../../../blobs/cpu/intel/model_6ex/microcode.h"
};

2
src/cpu/intel/model_6fx/microcode_blob.c
View File

@ -1,3 +1,3 @@
unsigned microcode_updates_6fx[] = {
#include "../../../../3rdparty/cpu/intel/model_6fx/microcode.h"
#include "../../../../blobs/cpu/intel/model_6fx/microcode.h"
};

2
src/cpu/intel/model_6xx/microcode_blob.c
View File

@ -1,3 +1,3 @@
unsigned microcode_updates_6xx[] = {
#include "../../../../3rdparty/cpu/intel/model_6xx/microcode.h"
#include "../../../../blobs/cpu/intel/model_6xx/microcode.h"
};

2
src/cpu/intel/model_f0x/microcode_blob.c
View File

@ -1,4 +1,4 @@
/* 256KB cache */
unsigned microcode_updates_f0x[] = {
#include "../../../../3rdparty/cpu/intel/model_f0x/microcode.h"
#include "../../../../blobs/cpu/intel/model_f0x/microcode.h"
};

2
src/cpu/intel/model_f1x/microcode_blob.c
View File

@ -1,4 +1,4 @@
/* 256KB cache */
unsigned microcode_updates_f1x[] = {
#include "../../../../3rdparty/cpu/intel/model_f1x/microcode.h"
#include "../../../../blobs/cpu/intel/model_f1x/microcode.h"
};

2
src/cpu/intel/model_f2x/microcode_blob.c
View File

@ -1,4 +1,4 @@
/* 512KB cache */
unsigned microcode_updates_f2x[] = {
#include "../../../../3rdparty/cpu/intel/model_f2x/microcode.h"
#include "../../../../blobs/cpu/intel/model_f2x/microcode.h"
};

2
src/cpu/intel/model_f3x/microcode_blob.c
View File

@ -1,3 +1,3 @@
unsigned microcode_updates_f3x[] = {
#include "../../../../3rdparty/cpu/intel/model_f3x/microcode.h"
#include "../../../../blobs/cpu/intel/model_f3x/microcode.h"
};

2
src/cpu/intel/model_f4x/microcode_blob.c
View File

@ -1,3 +1,3 @@
unsigned microcode_updates_f4x[] = {
#include "../../../../3rdparty/cpu/intel/model_f4x/microcode.h"
#include "../../../../blobs/cpu/intel/model_f4x/microcode.h"
};

2
src/cpu/samsung/exynos5250/update-bl1.sh
View File

@ -1,7 +1,7 @@
#!/bin/sh
BL1_NAME="E5250.nbl1.bin"
BL1_PATH="3rdparty/cpu/samsung/exynos5250/"
BL1_PATH="blobs/cpu/samsung/exynos5250/"
BL1_URL="http://commondatastorage.googleapis.com/chromeos-localmirror/distfiles/exynos-pre-boot-0.0.2-r8.tbz2"
get_bl1() {

2
src/mainboard/amd/lamar/Kconfig
View File

@ -79,7 +79,7 @@ config ONBOARD_VGA_IS_PRIMARY
config HUDSON_XHCI_FWM_FILE
string
default "3rdparty/southbridge/amd/bolton/xhci.bin"
default "blobs/southbridge/amd/bolton/xhci.bin"
config AZ_PIN
hex

2
src/northbridge/amd/pi/00630F01/Kconfig
View File

@ -48,6 +48,6 @@ config VGA_BIOS_ID
config VGA_BIOS_FILE
string
default "3rdparty/northbridge/amd/00630F01/VBIOS.bin"
default "blobs/northbridge/amd/00630F01/VBIOS.bin"
endif

2
src/northbridge/amd/pi/00730F01/Kconfig
View File

@ -49,6 +49,6 @@ config VGA_BIOS_ID
config VGA_BIOS_FILE
string
default "3rdparty/northbridge/amd/00730F01/VBIOS.bin"
default "blobs/northbridge/amd/00730F01/VBIOS.bin"
endif

2
src/northbridge/intel/sandybridge/Kconfig
View File

@ -105,7 +105,7 @@ config HAVE_MRC
config MRC_FILE
string "Intel System Agent path and filename"
depends on HAVE_MRC
default "3rdparty/northbridge/intel/sandybridge/systemagent-r6.bin"
default "blobs/northbridge/intel/sandybridge/systemagent-r6.bin"
help
The path and filename of the file to use as System Agent
binary.

8
src/soc/intel/baytrail/Kconfig
View File

@ -75,7 +75,7 @@ if HAVE_MRC
config MRC_FILE
string "Intel memory refeference code path and filename"
default "3rdparty/northbridge/intel/sandybridge/systemagent-r6.bin"
default "blobs/northbridge/intel/sandybridge/systemagent-r6.bin"
help
The path and filename of the file to use as System Agent
binary. Note that this points to the sandybridge binary file
@ -174,7 +174,7 @@ config HAVE_ME_BIN
help
The Intel processor in the selected system requires a special firmware
for an integrated controller called Management Engine (ME). The ME
firmware might be provided in coreboot's 3rdparty repository. If
firmware might be provided in coreboot's blobs repository. If
not and if you don't have the firmware elsewhere, you can still
build coreboot without it. In this case however, you'll have to make
sure that you don't overwrite your ME firmware on your flash ROM.
@ -182,7 +182,7 @@ config HAVE_ME_BIN
config ME_BIN_PATH
string "Path to management engine firmware"
depends on HAVE_ME_BIN
default "3rdparty/mainboard/$(MAINBOARDDIR)/me.bin"
default "blobs/mainboard/$(MAINBOARDDIR)/me.bin"
config HAVE_IFD_BIN
bool
@ -223,7 +223,7 @@ config IFD_PLATFORM_SECTION
config IFD_BIN_PATH
string "Path to intel firmware descriptor"
depends on !BUILD_WITH_FAKE_IFD
default "3rdparty/mainboard/$(MAINBOARDDIR)/descriptor.bin"
default "blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin"
config HAVE_REFCODE_BLOB
depends on ARCH_X86

2
src/soc/intel/baytrail/microcode/microcode_blob.c
View File

@ -1,3 +1,3 @@
unsigned microcode[] = {
#include "../../../../../3rdparty/soc/intel/baytrail/microcode_blob.h"
#include "../../../../../blobs/soc/intel/baytrail/microcode_blob.h"
};

6
src/soc/intel/broadwell/Kconfig
View File

@ -211,7 +211,7 @@ config HAVE_ME_BIN
help
The Intel processor in the selected system requires a special firmware
for an integrated controller called Management Engine (ME). The ME
firmware might be provided in coreboot's 3rdparty repository. If
firmware might be provided in coreboot's blobs repository. If
not and if you don't have the firmware elsewhere, you can still
build coreboot without it. In this case however, you'll have to make
sure that you don't overwrite your ME firmware on your flash ROM.
@ -219,7 +219,7 @@ config HAVE_ME_BIN
config ME_BIN_PATH
string "Path to management engine firmware"
depends on HAVE_ME_BIN
default "3rdparty/mainboard/$(MAINBOARDDIR)/me.bin"
default "blobs/mainboard/$(MAINBOARDDIR)/me.bin"
config HAVE_IFD_BIN
bool "Use Intel Firmware Descriptor from existing binary"
@ -260,7 +260,7 @@ config IFD_PLATFORM_SECTION
config IFD_BIN_PATH
string "Path to intel firmware descriptor"
depends on !BUILD_WITH_FAKE_IFD
default "3rdparty/mainboard/$(MAINBOARDDIR)/descriptor.bin"
default "blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin"
config LOCK_MANAGEMENT_ENGINE
bool "Lock Management Engine section"

2
src/soc/intel/broadwell/microcode/microcode_blob.c
View File

@ -18,6 +18,6 @@
*/
unsigned microcode[] = {
#include "../../../../../3rdparty/soc/intel/broadwell/microcode_blob.h"
#include "../../../../../blobs/soc/intel/broadwell/microcode_blob.h"
};

2
src/soc/nvidia/tegra132/Kconfig
View File

@ -49,7 +49,7 @@ config MAX_CPUS
config MTS_DIRECTORY
string "Directory where MTS microcode files are located"
default "3rdparty/cpu/nvidia/tegra132/current/prod"
default "blobs/cpu/nvidia/tegra132/current/prod"
help
Path to directory where MTS microcode files are located.

2
src/soc/qualcomm/ipq806x/Kconfig
View File

@ -30,7 +30,7 @@ config MBN_ENCAPSULATION
config SBL_BLOB
depends on USE_BLOBS
string "file name of the Qualcomm SBL blob"
default "3rdparty/cpu/qualcomm/ipq806x/uber-sbl.mbn"
default "blobs/cpu/qualcomm/ipq806x/uber-sbl.mbn"
help
The path and filename of the binary blob containing
ipq806x early initialization code, as supplied by the

2
src/soc/qualcomm/ipq806x/Makefile.inc
View File

@ -83,7 +83,7 @@ CPPFLAGS_common += -Isrc/soc/qualcomm/ipq806x/include
mbn-files := cdt.mbn ddr.mbn rpm.mbn tz.mbn
# Location of the binary blobs
mbn-root := 3rdparty/cpu/qualcomm/ipq806x
mbn-root := blobs/cpu/qualcomm/ipq806x
# Create make variables to aid cbfs-files-handler in processing the blobs (add
# them all as raw binaries at the root level).

2
src/soc/samsung/exynos5250/Makefile.inc
View File

@ -52,6 +52,6 @@ $(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf
$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
@printf " BL1, CKSUM $(subst $(obj)/,,$(@))\n"
util/exynos/fixed_cksum.py $< $<.cksum 32768
cat 3rdparty/cpu/samsung/exynos5250/bl1.bin $<.cksum > $@
cat blobs/cpu/samsung/exynos5250/bl1.bin $<.cksum > $@
endif

2
src/soc/samsung/exynos5420/Makefile.inc
View File

@ -54,6 +54,6 @@ $(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf
$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
@printf " BL1, CKSUM $(subst $(obj)/,,$(@))\n"
util/exynos/variable_cksum.py $< $<.cksum
cat 3rdparty/cpu/samsung/exynos5420/bl1.bin $<.cksum > $@
cat blobs/cpu/samsung/exynos5420/bl1.bin $<.cksum > $@
endif

12
src/southbridge/amd/agesa/hudson/Kconfig
View File

@ -74,20 +74,20 @@ config HUDSON_GEC_FWM
config HUDSON_XHCI_FWM_FILE
string "XHCI firmware path and filename"
default "3rdparty/southbridge/amd/hudson/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON
default "3rdparty/southbridge/amd/yangtze/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE
default "blobs/southbridge/amd/hudson/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON
default "blobs/southbridge/amd/yangtze/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE
depends on HUDSON_XHCI_FWM
config HUDSON_IMC_FWM_FILE
string "IMC firmware path and filename"
default "3rdparty/southbridge/amd/hudson/imc.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON
default "3rdparty/southbridge/amd/yangtze/imc.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE
default "blobs/southbridge/amd/hudson/imc.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON
default "blobs/southbridge/amd/yangtze/imc.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE
depends on HUDSON_IMC_FWM
config HUDSON_GEC_FWM_FILE
string "GEC firmware path and filename"
default "3rdparty/southbridge/amd/hudson/gec.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON
default "3rdparty/southbridge/amd/yangtze/gec.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE
default "blobs/southbridge/amd/hudson/gec.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON
default "blobs/southbridge/amd/yangtze/gec.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE
depends on HUDSON_GEC_FWM
config HUDSON_FWM

4
src/southbridge/amd/agesa/hudson/Makefile.inc
View File

@ -89,7 +89,7 @@ cbfs-files-y += hudson/xhci
hudson/xhci-file := $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE))
hudson/xhci-position := $(HUDSON_XHCI_POSITION)
hudson/xhci-type := raw
hudson/xhci-required := Hudson XHCI firmware (available in coreboot/3rdparty if enabled)
hudson/xhci-required := Hudson XHCI firmware (available in coreboot/blobs if enabled)
endif
ifeq ($(CONFIG_HUDSON_IMC_FWM), y)
@ -97,7 +97,7 @@ cbfs-files-y += hudson/imc
hudson/imc-file := $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE))
hudson/imc-position := $(HUDSON_IMC_POSITION)
hudson/imc-type := raw
hudson/imc-required := Hudson IMC Firmware (available in coreboot/3rdparty if enabled)
hudson/imc-required := Hudson IMC Firmware (available in coreboot/blobs if enabled)
endif
ifeq ($(CONFIG_HUDSON_GEC_FWM), y)

2
src/southbridge/amd/cimx/sb800/Kconfig
View File

@ -134,7 +134,7 @@ if SB800_IMC_FWM
config SB800_IMC_FWM_FILE
string "IMC firmware path and filename"
default "3rdparty/southbridge/amd/sb800/imc.bin"
default "blobs/southbridge/amd/sb800/imc.bin"
choice
prompt "SB800 Firmware ROM Position"

6
src/southbridge/amd/pi/hudson/Kconfig
View File

@ -83,12 +83,12 @@ config HUDSON_PSP
config HUDSON_XHCI_FWM_FILE
string "XHCI firmware path and filename"
default "3rdparty/southbridge/amd/avalon/xhci.bin" if SOUTHBRIDGE_AMD_PI_AVALON
default "blobs/southbridge/amd/avalon/xhci.bin" if SOUTHBRIDGE_AMD_PI_AVALON
depends on HUDSON_XHCI_FWM
config HUDSON_IMC_FWM_FILE
string "IMC firmware path and filename"
default "3rdparty/southbridge/amd/avalon/imc.bin" if SOUTHBRIDGE_AMD_PI_AVALON
default "blobs/southbridge/amd/avalon/imc.bin" if SOUTHBRIDGE_AMD_PI_AVALON
depends on HUDSON_IMC_FWM
config HUDSON_GEC_FWM_FILE
@ -126,7 +126,7 @@ endif # HUDSON_FWM
config AMD_PUBKEY_FILE
depends on HUDSON_PSP
string "AMD public Key"
default "3rdparty/southbridge/amd/avalon/PSP/AmdPubKey.bin" if CPU_AMD_PI_00730F01
default "blobs/southbridge/amd/avalon/PSP/AmdPubKey.bin" if CPU_AMD_PI_00730F01
config HUDSON_SATA_MODE
int "SATA Mode"

4
src/southbridge/amd/pi/hudson/Makefile.inc
View File

@ -133,7 +133,7 @@ cbfs-files-y += fch/xhci
fch/xhci-file := $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE))
fch/xhci-position := $(HUDSON_XHCI_POSITION)
fch/xhci-type := raw
fch/xhci-required := Hudson XHCI firmware (available in coreboot/3rdparty if enabled)
fch/xhci-required := Hudson XHCI firmware (available in coreboot/blobs if enabled)
endif
ifeq ($(CONFIG_HUDSON_IMC_FWM), y)
@ -141,7 +141,7 @@ cbfs-files-y += fch/imc
fch/imc-file := $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE))
fch/imc-position := $(HUDSON_IMC_POSITION)
fch/imc-type := raw
fch/imc-required := Hudson IMC Firmware (available in coreboot/3rdparty if enabled)
fch/imc-required := Hudson IMC Firmware (available in coreboot/blobs if enabled)
endif
ifeq ($(CONFIG_HUDSON_GEC_FWM), y)

8
src/southbridge/intel/bd82x6x/Kconfig
View File

@ -106,7 +106,7 @@ config IFD_PLATFORM_SECTION
config IFD_BIN_PATH
string "Path to intel firmware descriptor"
depends on !BUILD_WITH_FAKE_IFD
default "3rdparty/mainboard/$(MAINBOARDDIR)/descriptor.bin"
default "blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin"
config HAVE_GBE_BIN
bool "Add gigabit ethernet firmware"
@ -119,7 +119,7 @@ config HAVE_GBE_BIN
config GBE_BIN_PATH
string "Path to gigabit ethernet firmware"
depends on HAVE_GBE_BIN
default "3rdparty/mainboard/$(MAINBOARDDIR)/gbe.bin"
default "blobs/mainboard/$(MAINBOARDDIR)/gbe.bin"
config HAVE_ME_BIN
bool "Add Intel Management Engine firmware"
@ -127,7 +127,7 @@ config HAVE_ME_BIN
help
The Intel processor in the selected system requires a special firmware
for an integrated controller called Management Engine (ME). The ME
firmware might be provided in coreboot's 3rdparty repository. If
firmware might be provided in coreboot's blobs repository. If
not and if you don't have the firmware elsewhere, you can still
build coreboot without it. In this case however, you'll have to make
sure that you don't overwrite your ME firmware on your flash ROM.
@ -135,7 +135,7 @@ config HAVE_ME_BIN
config ME_BIN_PATH
string "Path to management engine firmware"
depends on HAVE_ME_BIN
default "3rdparty/mainboard/$(MAINBOARDDIR)/me.bin"
default "blobs/mainboard/$(MAINBOARDDIR)/me.bin"
config LOCK_MANAGEMENT_ENGINE
bool "Lock Management Engine section"

6
src/southbridge/intel/ibexpeak/Kconfig
View File

@ -87,7 +87,7 @@ config IFD_ME_SECTION
config IFD_BIN_PATH
string "Path to intel firmware descriptor"
depends on !BUILD_WITH_FAKE_IFD
default "3rdparty/mainboard/$(MAINBOARDDIR)/descriptor.bin"
default "blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin"
config HAVE_ME_BIN
@ -96,7 +96,7 @@ config HAVE_ME_BIN
help
The Intel processor in the selected system requires a special firmware
for an integrated controller called Management Engine (ME). The ME
firmware might be provided in coreboot's 3rdparty repository. If
firmware might be provided in coreboot's blobs repository. If
not and if you don't have the firmware elsewhere, you can still
build coreboot without it. In this case however, you'll have to make
sure that you don't overwrite your ME firmware on your flash ROM.
@ -104,7 +104,7 @@ config HAVE_ME_BIN
config ME_BIN_PATH
string "Path to management engine firmware"
depends on HAVE_ME_BIN
default "3rdparty/mainboard/$(MAINBOARDDIR)/me.bin"
default "blobs/mainboard/$(MAINBOARDDIR)/me.bin"
config HPET_MIN_TICKS
hex

6
src/southbridge/intel/lynxpoint/Kconfig
View File

@ -98,7 +98,7 @@ config IFD_PLATFORM_SECTION
config IFD_BIN_PATH
string "Path to intel firmware descriptor"
depends on !BUILD_WITH_FAKE_IFD
default "3rdparty/mainboard/$(MAINBOARDDIR)/descriptor.bin"
default "blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin"
config HAVE_ME_BIN
bool "Add Intel Management Engine firmware"
@ -106,7 +106,7 @@ config HAVE_ME_BIN
help
The Intel processor in the selected system requires a special firmware
for an integrated controller called Management Engine (ME). The ME
firmware might be provided in coreboot's 3rdparty repository. If
firmware might be provided in coreboot's blobs repository. If
not and if you don't have the firmware elsewhere, you can still
build coreboot without it. In this case however, you'll have to make
sure that you don't overwrite your ME firmware on your flash ROM.
@ -114,7 +114,7 @@ config HAVE_ME_BIN
config ME_BIN_PATH
string "Path to management engine firmware"
depends on HAVE_ME_BIN
default "3rdparty/mainboard/$(MAINBOARDDIR)/me.bin"
default "blobs/mainboard/$(MAINBOARDDIR)/me.bin"
config ME_MBP_CLEAR_LATE
bool "Defer wait for ME MBP Cleared"

2
src/vendorcode/amd/Kconfig
View File

@ -37,7 +37,7 @@ config CPU_AMD_AGESA_BINARY_PI
select HUDSON_DISABLE_IMC
help
Use a binary PI package. Generally, these will be stored in the
"3rdparty" directory. For some processors, these must be obtained
"blobs" directory. For some processors, these must be obtained
directly from AMD Embedded Processors Group
(http://www.amdcom/embedded).

2
src/vendorcode/amd/pi/00630F01/Kconfig
View File

@ -35,7 +35,7 @@ config AGESA_BINARY_PI_DEFAULTS # dummy
config AGESA_BINARY_PI_PATH_DEFAULT
string
default "3rdparty/pi/amd/00630F01"
default "blobs/pi/amd/00630F01"
help
The default binary file name to use for AMD platform initialization.

2
src/vendorcode/amd/pi/00730F01/Kconfig
View File

@ -35,7 +35,7 @@ config AGESA_BINARY_PI_DEFAULTS # dummy
config AGESA_BINARY_PI_PATH_DEFAULT
string
default "3rdparty/pi/amd/00730F01"
default "blobs/pi/amd/00730F01"
help
The default binary file name to use for AMD platform initialization.

2
src/vendorcode/google/chromeos/build-snow
View File

@ -8,7 +8,7 @@ TMP_DIFF="$SCRIPT_DIR/.image-diff.bin"
FLASHROM="/usr/local/sbin/flashrom"
BL1_NAME="E5250.nbl1.bin"
BL1_PATH="3rdparty/cpu/samsung/exynos5250/"
BL1_PATH="blobs/cpu/samsung/exynos5250/"
BL1_URL="http://commondatastorage.googleapis.com/chromeos-localmirror/distfiles/exynos-pre-boot-0.0.2-r8.tbz2"
die() {