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nb/intel/haswell: Deduplicate PCIEXBAR decoding 

Add `decode_pcie_bar` for consistency with other Intel northbridges.

Change-Id: If04ca3467bb067b28605a3acccb8bda325735999
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Angel Pons 2020-08-03 14:12:13 +02:00
parent 90de10c17a
commit f4fa1e1d06
3 changed files with 11 additions and 35 deletions
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39
src/northbridge/intel/haswell/acpi.c
View File

@ -2,6 +2,7 @@
#include <types.h> #include <types.h>
#include <console/console.h> #include <console/console.h>
#include <commonlib/helpers.h>
#include <acpi/acpi.h> #include <acpi/acpi.h>
#include <device/device.h> #include <device/device.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
@ -10,44 +11,12 @@
unsigned long acpi_fill_mcfg(unsigned long current) unsigned long acpi_fill_mcfg(unsigned long current)
{ {
struct device *dev; u32 length, pciexbar;
u32 pciexbar = 0;
u32 pciexbar_reg;
int max_buses;
u32 mask;
dev = pcidev_on_root(0, 0); if (!decode_pcie_bar(&pciexbar, &length))
if (!dev)
return current; return current;
pciexbar_reg = pci_read_config32(dev, PCIEXBAR); const int max_buses = length / MiB;
/* MMCFG not supported or not enabled. */
if (!(pciexbar_reg & (1 << 0)))
return current;
mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28);
switch ((pciexbar_reg >> 1) & 3) {
case 0: /* 256MB */
pciexbar = pciexbar_reg & mask;
max_buses = 256;
break;
case 1: /* 128M */
mask |= (1 << 27);
pciexbar = pciexbar_reg & mask;
max_buses = 128;
break;
case 2: /* 64M */
mask |= (1 << 27) | (1 << 26);
pciexbar = pciexbar_reg & mask;
max_buses = 64;
break;
default: /* RSVD */
return current;
}
if (!pciexbar)
return current;
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, pciexbar, 0, 0, current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, pciexbar, 0, 0,
max_buses - 1); max_buses - 1);

2
src/northbridge/intel/haswell/haswell.h
View File

@ -157,6 +157,8 @@ void haswell_unhide_peg(void);
void report_platform_info(void); void report_platform_info(void);
int decode_pcie_bar(u32 *const base, u32 *const len);
#include <device/device.h> #include <device/device.h>
struct acpi_rsdp; struct acpi_rsdp;

5
src/northbridge/intel/haswell/northbridge.c
View File

@ -51,6 +51,11 @@ static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 *
return 0; return 0;
} }
int decode_pcie_bar(u32 *const base, u32 *const len)
{
return get_pcie_bar(pcidev_on_root(0, 0), PCIEXBAR, base, len);
}
static const char *northbridge_acpi_name(const struct device *dev) static const char *northbridge_acpi_name(const struct device *dev)
{ {
if (dev->path.type == DEVICE_PATH_DOMAIN) if (dev->path.type == DEVICE_PATH_DOMAIN)