soc/intel/skylake: Limit xDCI feature when VBOOT is enabled
Use the common xDCI function to check if the controller is allowed in the current mode before enabling it. Otherwise, disable the PCI device if it has been enabled in devicetree. To make the SOC behavior consistent the XdciEnable config option is removed in favor of direct control by devicetree.cb and the mainboards that had defined it were adjusted accordingly. This was tested on an Eve board with xDCI enabled in devicetree.cb to ensure the xDCI device is enabled in developer mode and disabled in normal mode. Change-Id: Ic3c84beac87452f17490de32082030880834501d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/25365 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -36,7 +36,6 @@ chip soc/intel/skylake
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register "DspEnable" = "1"
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register "IoBufferOwnership" = "3"
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register "EnableTraceHub" = "0"
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register "XdciEnable" = "0"
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register "SsicPortEnable" = "0"
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register "SmbusEnable" = "1"
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register "Cio2Enable" = "0"
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@ -32,7 +32,6 @@ chip soc/intel/skylake
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register "DspEnable" = "1"
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register "IoBufferOwnership" = "3"
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register "EnableTraceHub" = "0"
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register "XdciEnable" = "0"
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register "SsicPortEnable" = "0"
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register "SmbusEnable" = "1"
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register "Cio2Enable" = "0"
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@ -67,7 +67,6 @@ chip soc/intel/skylake
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register "DspEnable" = "1"
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register "IoBufferOwnership" = "3"
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register "EnableTraceHub" = "0"
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register "XdciEnable" = "0"
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register "SsicPortEnable" = "0"
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register "SmbusEnable" = "1"
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register "Cio2Enable" = "0"
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@ -36,7 +36,6 @@ chip soc/intel/skylake
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register "DspEnable" = "1"
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register "IoBufferOwnership" = "3"
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register "EnableTraceHub" = "0"
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register "XdciEnable" = "0"
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register "SsicPortEnable" = "0"
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register "SmbusEnable" = "1"
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register "Cio2Enable" = "0"
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@ -38,7 +38,6 @@ chip soc/intel/skylake
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register "DspEnable" = "1"
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register "IoBufferOwnership" = "3"
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register "EnableTraceHub" = "0"
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register "XdciEnable" = "0"
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register "SsicPortEnable" = "0"
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register "SmbusEnable" = "1"
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register "Cio2Enable" = "1"
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@ -34,7 +34,6 @@ chip soc/intel/skylake
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register "DspEnable" = "1"
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register "IoBufferOwnership" = "3"
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register "EnableTraceHub" = "0"
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register "XdciEnable" = "0"
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register "SsicPortEnable" = "0"
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register "SmbusEnable" = "1"
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register "Cio2Enable" = "0"
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@ -38,7 +38,6 @@ chip soc/intel/skylake
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register "DspEnable" = "1"
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register "IoBufferOwnership" = "3"
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register "EnableTraceHub" = "0"
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register "XdciEnable" = "0"
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register "SsicPortEnable" = "0"
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register "SmbusEnable" = "1"
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register "Cio2Enable" = "1"
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@ -38,7 +38,6 @@ chip soc/intel/skylake
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register "DspEnable" = "1"
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register "IoBufferOwnership" = "3"
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register "EnableTraceHub" = "0"
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register "XdciEnable" = "0"
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register "SsicPortEnable" = "0"
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register "SmbusEnable" = "1"
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register "Cio2Enable" = "1"
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@ -170,7 +170,6 @@ chip soc/intel/skylake
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# USB related
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register "SsicPortEnable" = "1"
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register "XdciEnable" = "0"
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register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # OTG
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register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Touch Pad
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@ -41,7 +41,6 @@ chip soc/intel/skylake
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register "DspEnable" = "0"
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register "IoBufferOwnership" = "0"
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register "EnableTraceHub" = "0"
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register "XdciEnable" = "0"
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register "SsicPortEnable" = "0"
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register "SmbusEnable" = "1"
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register "Cio2Enable" = "0"
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@ -41,7 +41,6 @@ chip soc/intel/skylake
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register "DspEnable" = "0"
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register "IoBufferOwnership" = "0"
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register "EnableTraceHub" = "0"
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register "XdciEnable" = "0"
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register "SsicPortEnable" = "0"
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register "SmbusEnable" = "1"
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register "Cio2Enable" = "0"
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@ -85,6 +85,7 @@ config CPU_SPECIFIC_OPTIONS
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select SOC_INTEL_COMMON_BLOCK_TIMER
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select SOC_INTEL_COMMON_BLOCK_UART
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select SOC_INTEL_COMMON_BLOCK_VMX
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select SOC_INTEL_COMMON_BLOCK_XDCI
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select SOC_INTEL_COMMON_BLOCK_XHCI
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select SOC_INTEL_COMMON_GFX_OPREGION
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select SOC_INTEL_COMMON_NHLT
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@ -20,6 +20,7 @@
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#include <device/device.h>
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#include <device/pci.h>
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#include <fsp/util.h>
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#include <intelblocks/xdci.h>
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#include <soc/acpi.h>
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#include <soc/interrupt.h>
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#include <soc/irq.h>
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@ -78,7 +79,7 @@ struct chip_operations soc_intel_skylake_ops = {
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/* UPD parameters to be initialized before SiliconInit */
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void soc_silicon_init_params(SILICON_INIT_UPD *params)
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{
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const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
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struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
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const struct soc_intel_skylake_config *config = dev->chip_info;
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int i;
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@ -140,7 +141,6 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
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params->EnableAzalia = config->EnableAzalia;
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params->IoBufferOwnership = config->IoBufferOwnership;
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params->DspEnable = config->DspEnable;
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params->XdciEnable = config->XdciEnable;
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params->Device4Enable = config->Device4Enable;
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params->EnableSata = config->EnableSata;
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params->SataMode = config->SataMode;
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@ -196,6 +196,12 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
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dev = dev_find_slot(0, PCH_DEVFN_SPI);
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params->ShowSpiController = dev->enabled;
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/* Enable xDCI controller if enabled in devicetree and allowed */
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dev = dev_find_slot(0, PCH_DEVFN_USBOTG);
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if (!xdci_can_enable())
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dev->enabled = 0;
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params->XdciEnable = dev->enabled;
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params->SendVrMbxCmd = config->SendVrMbxCmd;
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/* Acoustic Noise Mitigation */
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@ -237,7 +237,6 @@ struct soc_intel_skylake_config {
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/* USB related */
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struct usb2_port_config usb2_ports[16];
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struct usb3_port_config usb3_ports[10];
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u8 XdciEnable;
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u8 SsicPortEnable;
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/* SMBus */
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@ -26,6 +26,7 @@
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#include <device/pci.h>
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#include <fsp/api.h>
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#include <fsp/util.h>
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#include <intelblocks/xdci.h>
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#include <romstage_handoff.h>
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#include <soc/acpi.h>
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#include <soc/intel/common/vbt.h>
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@ -221,7 +222,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
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params->PchHdaEnable = config->EnableAzalia;
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params->PchHdaIoBufferOwnership = config->IoBufferOwnership;
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params->PchHdaDspEnable = config->DspEnable;
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params->XdciEnable = config->XdciEnable;
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params->Device4Enable = config->Device4Enable;
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params->SataEnable = config->EnableSata;
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params->SataMode = config->SataMode;
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@ -284,6 +284,12 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
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dev = dev_find_slot(0, PCH_DEVFN_SPI);
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params->ShowSpiController = dev->enabled;
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/* Enable xDCI controller if enabled in devicetree and allowed */
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dev = dev_find_slot(0, PCH_DEVFN_USBOTG);
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if (!xdci_can_enable())
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dev->enabled = 0;
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params->XdciEnable = dev->enabled;
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/*
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* Send VR specific mailbox commands:
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* 000b - no VR specific command sent
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