soc/intel/skylake: Limit xDCI feature when VBOOT is enabled

Use the common xDCI function to check if the controller is allowed
in the current mode before enabling it.  Otherwise, disable the
PCI device if it has been enabled in devicetree.

To make the SOC behavior consistent the XdciEnable config option
is removed in favor of direct control by devicetree.cb and the
mainboards that had defined it were adjusted accordingly.

This was tested on an Eve board with xDCI enabled in devicetree.cb
to ensure the xDCI device is enabled in developer mode and disabled
in normal mode.

Change-Id: Ic3c84beac87452f17490de32082030880834501d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/25365
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/chell/devicetree.cb

@@ -36,7 +36,6 @@ chip soc/intel/skylake
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
 	register "EnableTraceHub" = "0"
-	register "XdciEnable" = "0"
 	register "SsicPortEnable" = "0"
 	register "SmbusEnable" = "1"
 	register "Cio2Enable" = "0"

src/mainboard/google/eve/devicetree.cb

@@ -32,7 +32,6 @@ chip soc/intel/skylake
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
 	register "EnableTraceHub" = "0"
-	register "XdciEnable" = "0"
 	register "SsicPortEnable" = "0"
 	register "SmbusEnable" = "1"
 	register "Cio2Enable" = "0"

src/mainboard/google/fizz/devicetree.cb

@@ -67,7 +67,6 @@ chip soc/intel/skylake
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
 	register "EnableTraceHub" = "0"
-	register "XdciEnable" = "0"
 	register "SsicPortEnable" = "0"
 	register "SmbusEnable" = "1"
 	register "Cio2Enable" = "0"

src/mainboard/google/glados/devicetree.cb

@@ -36,7 +36,6 @@ chip soc/intel/skylake
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
 	register "EnableTraceHub" = "0"
-	register "XdciEnable" = "0"
 	register "SsicPortEnable" = "0"
 	register "SmbusEnable" = "1"
 	register "Cio2Enable" = "0"

src/mainboard/google/poppy/variants/baseboard/devicetree.cb

@@ -38,7 +38,6 @@ chip soc/intel/skylake
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
 	register "EnableTraceHub" = "0"
-	register "XdciEnable" = "0"
 	register "SsicPortEnable" = "0"
 	register "SmbusEnable" = "1"
 	register "Cio2Enable" = "1"

src/mainboard/google/poppy/variants/nami/devicetree.cb

@@ -34,7 +34,6 @@ chip soc/intel/skylake
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
 	register "EnableTraceHub" = "0"
-	register "XdciEnable" = "0"
 	register "SsicPortEnable" = "0"
 	register "SmbusEnable" = "1"
 	register "Cio2Enable" = "0"

src/mainboard/google/poppy/variants/nautilus/devicetree.cb

@@ -38,7 +38,6 @@ chip soc/intel/skylake
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
 	register "EnableTraceHub" = "0"
-	register "XdciEnable" = "0"
 	register "SsicPortEnable" = "0"
 	register "SmbusEnable" = "1"
 	register "Cio2Enable" = "1"

src/mainboard/google/poppy/variants/soraka/devicetree.cb

@@ -38,7 +38,6 @@ chip soc/intel/skylake
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
 	register "EnableTraceHub" = "0"
-	register "XdciEnable" = "0"
 	register "SsicPortEnable" = "0"
 	register "SmbusEnable" = "1"
 	register "Cio2Enable" = "1"

src/mainboard/intel/saddlebrook/devicetree.cb

@@ -170,7 +170,6 @@ chip soc/intel/skylake
 
 	# USB related
 	register "SsicPortEnable" = "1"
-	register "XdciEnable" = "0"
 
 	register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)"  # OTG
 	register "usb2_ports[1]" = "USB2_PORT_MID(OC3)"  # Touch Pad

src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb

@@ -41,7 +41,6 @@ chip soc/intel/skylake
 	register "DspEnable" = "0"
 	register "IoBufferOwnership" = "0"
 	register "EnableTraceHub" = "0"
-	register "XdciEnable" = "0"
 	register "SsicPortEnable" = "0"
 	register "SmbusEnable" = "1"
 	register "Cio2Enable" = "0"

src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb

@@ -41,7 +41,6 @@ chip soc/intel/skylake
 	register "DspEnable" = "0"
 	register "IoBufferOwnership" = "0"
 	register "EnableTraceHub" = "0"
-	register "XdciEnable" = "0"
 	register "SsicPortEnable" = "0"
 	register "SmbusEnable" = "1"
 	register "Cio2Enable" = "0"

src/soc/intel/skylake/Kconfig

@@ -85,6 +85,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_BLOCK_TIMER
 	select SOC_INTEL_COMMON_BLOCK_UART
 	select SOC_INTEL_COMMON_BLOCK_VMX
+	select SOC_INTEL_COMMON_BLOCK_XDCI
 	select SOC_INTEL_COMMON_BLOCK_XHCI
 	select SOC_INTEL_COMMON_GFX_OPREGION
 	select SOC_INTEL_COMMON_NHLT

src/soc/intel/skylake/chip.c

@@ -20,6 +20,7 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <fsp/util.h>
+#include <intelblocks/xdci.h>
 #include <soc/acpi.h>
 #include <soc/interrupt.h>
 #include <soc/irq.h>
@@ -78,7 +79,7 @@ struct chip_operations soc_intel_skylake_ops = {
 /* UPD parameters to be initialized before SiliconInit */
 void soc_silicon_init_params(SILICON_INIT_UPD *params)
 {
-	const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
+	struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
 	const struct soc_intel_skylake_config *config = dev->chip_info;
 	int i;
 
@@ -140,7 +141,6 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
 	params->EnableAzalia = config->EnableAzalia;
 	params->IoBufferOwnership = config->IoBufferOwnership;
 	params->DspEnable = config->DspEnable;
-	params->XdciEnable = config->XdciEnable;
 	params->Device4Enable = config->Device4Enable;
 	params->EnableSata = config->EnableSata;
 	params->SataMode = config->SataMode;
@@ -196,6 +196,12 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
 	dev = dev_find_slot(0, PCH_DEVFN_SPI);
 	params->ShowSpiController = dev->enabled;
 
+	/* Enable xDCI controller if enabled in devicetree and allowed */
+	dev = dev_find_slot(0, PCH_DEVFN_USBOTG);
+	if (!xdci_can_enable())
+		dev->enabled = 0;
+	params->XdciEnable = dev->enabled;
+
 	params->SendVrMbxCmd = config->SendVrMbxCmd;
 
 	/* Acoustic Noise Mitigation */

src/soc/intel/skylake/chip.h

@@ -237,7 +237,6 @@ struct soc_intel_skylake_config {
 	/* USB related */
 	struct usb2_port_config usb2_ports[16];
 	struct usb3_port_config usb3_ports[10];
-	u8 XdciEnable;
 	u8 SsicPortEnable;
 
 	/* SMBus */

src/soc/intel/skylake/chip_fsp20.c

@@ -26,6 +26,7 @@
 #include <device/pci.h>
 #include <fsp/api.h>
 #include <fsp/util.h>
+#include <intelblocks/xdci.h>
 #include <romstage_handoff.h>
 #include <soc/acpi.h>
 #include <soc/intel/common/vbt.h>
@@ -221,7 +222,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	params->PchHdaEnable = config->EnableAzalia;
 	params->PchHdaIoBufferOwnership = config->IoBufferOwnership;
 	params->PchHdaDspEnable = config->DspEnable;
-	params->XdciEnable = config->XdciEnable;
 	params->Device4Enable = config->Device4Enable;
 	params->SataEnable = config->EnableSata;
 	params->SataMode = config->SataMode;
@@ -284,6 +284,12 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	dev = dev_find_slot(0, PCH_DEVFN_SPI);
 	params->ShowSpiController = dev->enabled;
 
+	/* Enable xDCI controller if enabled in devicetree and allowed */
+	dev = dev_find_slot(0, PCH_DEVFN_USBOTG);
+	if (!xdci_can_enable())
+		dev->enabled = 0;
+	params->XdciEnable = dev->enabled;
+
 	/*
 	 * Send VR specific mailbox commands:
 	 * 000b - no VR specific command sent