soc/amd/cezanne: Add PSP integration for cezanne
Change-Id: Ifa69f03b4c7b871a9f018f40930d2382d2154403 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48528 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Zheng Bao
Felix Held
parent
7a5c369614
commit
f51738ddab
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@ -118,4 +118,73 @@ config CONSOLE_UART_BASE_ADDRESS
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default 0xfedc9000 if UART_FOR_CONSOLE = 0
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default 0xfedca000 if UART_FOR_CONSOLE = 1
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menu "PSP Configuration Options"
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config AMD_FWM_POSITION_INDEX
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int "Firmware Directory Table location (0 to 5)"
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range 0 5
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default 0 if BOARD_ROMSIZE_KB_512
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default 1 if BOARD_ROMSIZE_KB_1024
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default 2 if BOARD_ROMSIZE_KB_2048
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default 3 if BOARD_ROMSIZE_KB_4096
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default 4 if BOARD_ROMSIZE_KB_8192
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default 5 if BOARD_ROMSIZE_KB_16384
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help
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Typically this is calculated by the ROM size, but there may
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be situations where you want to put the firmware directory
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table in a different location.
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0: 512 KB - 0xFFFA0000
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1: 1 MB - 0xFFF20000
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2: 2 MB - 0xFFE20000
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3: 4 MB - 0xFFC20000
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4: 8 MB - 0xFF820000
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5: 16 MB - 0xFF020000
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comment "AMD Firmware Directory Table set to location for 512KB ROM"
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depends on AMD_FWM_POSITION_INDEX = 0
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comment "AMD Firmware Directory Table set to location for 1MB ROM"
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depends on AMD_FWM_POSITION_INDEX = 1
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comment "AMD Firmware Directory Table set to location for 2MB ROM"
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depends on AMD_FWM_POSITION_INDEX = 2
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comment "AMD Firmware Directory Table set to location for 4MB ROM"
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depends on AMD_FWM_POSITION_INDEX = 3
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comment "AMD Firmware Directory Table set to location for 8MB ROM"
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depends on AMD_FWM_POSITION_INDEX = 4
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comment "AMD Firmware Directory Table set to location for 16MB ROM"
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depends on AMD_FWM_POSITION_INDEX = 5
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config AMDFW_CONFIG_FILE
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string
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default "src/soc/amd/cezanne/fw.cfg"
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config USE_PSPSECUREOS
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bool
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default y
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help
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Include the PspSecureOs and PspTrustlet binaries in the PSP build.
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If unsure, answer 'y'
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config PSP_LOAD_MP2_FW
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bool
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default n
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help
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Include the MP2 firmwares and configuration into the PSP build.
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If unsure, answer 'n'
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config PSP_LOAD_S0I3_FW
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bool
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default n
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help
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Select this item to include the S0i3 file into the PSP build.
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config PSP_UNLOCK_SECURE_DEBUG
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bool "Unlock secure debug"
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default y
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help
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Select this item to enable secure debug options in PSP.
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endmenu
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endif # SOC_AMD_CEZANNE
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@ -31,4 +31,149 @@ ramstage-y += uart.c
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CPPFLAGS_common += -I$(src)/soc/amd/cezanne/include
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MAINBOARD_BLOBS_DIR:=$(top)/3rdparty/blobs/mainboard/$(MAINBOARDDIR)
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# ROMSIG Normally At ROMBASE + 0x20000
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# Overridden by CONFIG_AMD_FWM_POSITION_INDEX
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# +-----------+---------------+----------------+------------+
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# |0x55AA55AA | | | |
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# +-----------+---------------+----------------+------------+
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# | | PSPDIR ADDR | BIOSDIR ADDR |
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# +-----------+---------------+----------------+
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CEZANNE_FWM_POSITION=$(call int-add, \
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$(call int-subtract, 0xffffffff \
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$(call int-shift-left, \
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0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000 1)
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#
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# PSP Directory Table items
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#
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# Certain ordering requirements apply, however these are ensured by amdfwtool.
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# For more information see "AMD Platform Security Processor BIOS Architecture
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# Design Guide for AMD Family 17h Processors" (PID #55758, NDA only).
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#
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FIRMWARE_LOCATION=$(shell grep -e FIRMWARE_LOCATION $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}')
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ifeq ($(CONFIG_PSP_UNLOCK_SECURE_DEBUG),y)
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# Enable secure debug unlock
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PSP_SOFTFUSE_BITS += 0
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OPT_TOKEN_UNLOCK="--token-unlock"
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endif
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ifeq ($(CONFIG_USE_PSPSECUREOS),y)
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# types = 0x2
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OPT_PSP_USE_PSPSECUREOS="--use-pspsecureos"
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endif
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ifeq ($(CONFIG_PSP_LOAD_MP2_FW),y)
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OPT_PSP_LOAD_MP2_FW="--load-mp2-fw"
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else
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# Disable MP2 firmware loading
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PSP_SOFTFUSE_BITS += 29
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endif
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ifeq ($(CONFIG_PSP_LOAD_S0I3_FW),y)
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OPT_PSP_LOAD_S0I3_FW="--load-s0i3"
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endif
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#
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# BIOS Directory Table items - proper ordering is managed by amdfwtool
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#
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# type = 0x60
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PSP_APCB_FILES=$(APCB_SOURCES) $(APCB_SOURCES_68) $(APCB_SOURCES_RECOVERY)
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# type = 0x61
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PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS)
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# type = 0x62
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PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img
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PSP_ELF_FILE=$(objcbfs)/bootblock.elf
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PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}')
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PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}')
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# type = 0x66
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# type = 0xb - See #55758 (NDA) for bit definitions.
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PSP_SOFTFUSE_BITS += 28
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#hardcode post code to eSPI
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PSP_SOFTFUSE_BITS += 15 6
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# Helper function to return a value with given bit set
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set-bit=$(call int-shift-left, 1 $(call _toint,$1))
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PSP_SOFTFUSE=$(shell A=$(call int-add, \
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$(foreach bit,$(PSP_SOFTFUSE_BITS),$(call set-bit,$(bit)))); printf "0x%x" $$A)
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#
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# Build the arguments to amdfwtool (order is unimportant). Missing file names
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# result in empty OPT_ variables, i.e. the argument is not passed to amdfwtool.
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#
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add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), )
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OPT_PSP_APCB_FILES= $(if $(APCB_SOURCES), --instance 0 --apcb $(APCB_SOURCES)) \
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$(if $(APCB_SOURCES_RECOVERY), --instance 10 --apcb $(APCB_SOURCES_RECOVERY)) \
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$(if $(APCB_SOURCES_68), --instance 18 --apcb $(APCB_SOURCES_68))
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OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base)
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OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin)
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OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest)
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OPT_PSP_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size)
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OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode)
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OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed)
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OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), --spi-micron-flag)
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OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse)
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# Add all the files listed in the config file
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POUND_SIGN=$(call strip_quotes, "\#")
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DEP_FILES= $(patsubst %,$(FIRMWARE_LOCATION)/%, $(shell sed -e /^$(POUND_SIGN)/d -e /*/d -e /^FIRMWARE_LOCATION/d $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}' ))
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AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \
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$(OPT_APOB_ADDR) \
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$(OPT_PSP_BIOSBIN_FILE) \
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$(OPT_PSP_BIOSBIN_DEST) \
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$(OPT_PSP_BIOSBIN_SIZE) \
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$(OPT_PSP_SOFTFUSE) \
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$(OPT_PSP_USE_PSPSECUREOS) \
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$(OPT_PSP_LOAD_MP2_FW) \
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$(OPT_PSP_LOAD_S0I3_FW) \
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--combo-capable \
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$(OPT_TOKEN_UNLOCK) \
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$(OPT_EFS_SPI_READ_MODE) \
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$(OPT_EFS_SPI_SPEED) \
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$(OPT_EFS_SPI_MICRON_FLAG) \
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--config $(CONFIG_AMDFW_CONFIG_FILE) \
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--soc-name "Cezanne" \
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--flashsize $(CONFIG_ROM_SIZE)
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$(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \
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$$(PSP_APCB_FILES) \
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$(DEP_FILES) \
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$(AMDFWTOOL) \
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$(obj)/fmap_config.h
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$(if $(PSP_APCB_FILES), ,$(error APCB_SOURCES is not set))
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rm -f $@
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@printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n"
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$(AMDFWTOOL) \
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$(AMDFW_COMMON_ARGS) \
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--location $(shell printf "%#x" $(CEZANNE_FWM_POSITION)) \
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--multilevel \
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--output $@
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$(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS)
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rm -f $@
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@printf " AMDCOMPRS $(subst $(obj)/,,$(@))\n"
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$(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ --compress \
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--maxsize $(PSP_BIOSBIN_SIZE)
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cbfs-files-y += apu/amdfw
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apu/amdfw-file := $(obj)/amdfw.rom
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apu/amdfw-position := $(CEZANNE_FWM_POSITION)
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apu/amdfw-type := raw
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endif # ($(CONFIG_SOC_AMD_CEZANNE),y)
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@ -0,0 +1,38 @@
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# PSP fw config file
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FIRMWARE_LOCATION 3rdparty/amd_blobs/cezanne/PSP
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# type file
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# PSP
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AMD_PUBKEY_FILE TypeId0x00_CezannePublicKey.tkn
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PSPBTLDR_FILE TypeId0x01_PspBootLoader_CZN.sbin
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PSPSECUREOS_FILE TypeId0x02_PspOS_CZN.sbin
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PSPRCVR_FILE TypeId0x03_PspRecoveryBootLoader_CZN.sbin
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PSP_SMUFW1_SUB0_FILE TypeId0x08_SmuFirmware_CZN.csbin
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PSPSECUREDEBUG_FILE TypeId0x09_SecureDebugUnlockKey_CZN.stkn
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PSPTRUSTLETS_FILE TypeId0x0C_FtpmDrv_CZN.csbin
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PSP_SMUFW2_SUB0_FILE TypeId0x12_SmuFirmware2_CZN.csbin
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PSP_SEC_DEBUG_FILE TypeId0x13_PspEarlyUnlock_CZN.sbin
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PSP_HW_IPCFG_FILE TypeId0x20_HwIpCfg_CZN_A0.sbin
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PSP_IKEK_FILE TypeId0x21_PspIkek_CZN.bin
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PSP_SECG0_FILE TypeId0x24_SecurePolicyL0_CZN.sbin
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PSP_MP2FW0_FILE TypeId0x25_Mp2Fw_CZN.sbin
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AMD_DRIVER_ENTRIES TypeId0x28_PspSystemDriver_CZN.sbin
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PSP_KVM_ENGINE_DUMMY_FILE TypeId0x29_KvmEngineDummy.csbin
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PSP_S0I3_FILE TypeId0x2D_AgesaRunTimeDrv_CZN.sbin
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PSP_ABL0_FILE TypeId0x30_AgesaBootloaderU_CZN_LPDDR4.csbin
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VBIOS_BTLOADER_FILE TypeId0x3C_VbiosBootLoader_CZN.sbin
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SECURE_POLICY_L1_FILE TypeId0x45_SecurePolicyL1_CZN.sbin
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UNIFIEDUSB_FILE TypeId0x44_UnifiedUsb_CZN.sbin
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DRTMTA_FILE TypeId0x47_DrtmTA_CZN.sbin
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KEYDBBL_FILE TypeId0x50_KeyDbBl_CZN.sbin
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KEYDB_TOS_FILE TypeId0x51_KeyDbTos_CZN.sbin
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DMCUERAMDCN21_FILE TypeId0x58_DmcuEramDcn21.sbin
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DMCUINTVECTORSDCN21_FILE TypeId0x59_DmcuIntvectorsDcn21.sbin
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# BDT
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PSP_PMUI_FILE1 TypeId0x64_Appb_CZN_1D_Lpddr4_Imem.csbin
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PSP_PMUD_FILE1 TypeId0x65_Appb_CZN_1D_Lpddr4_Dmem.csbin
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PSP_PMUI_FILE2 TypeId0x64_Appb_CZN_2D_Lpddr4_Imem.csbin
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PSP_PMUD_FILE2 TypeId0x65_Appb_CZN_2D_Lpddr4_Dmem.csbin
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PSP_MP2CFG_FILE MP2FWConfig.sbin
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