soc/apollolake: Add skeleton ACPI entry

Change-Id: Ib127af5392ca2b349480f5b21fad2186b444d7e6
Signed-off-by: Lance Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/13348
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/mainboard/intel/apollolake_rvp/Kconfig

@@ -4,6 +4,7 @@ config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select SOC_INTEL_APOLLOLAKE
 	select BOARD_ROMSIZE_KB_8192
+	select HAVE_ACPI_TABLES
 
 config MAINBOARD_DIR
 	string

src/mainboard/intel/apollolake_rvp/acpi_tables.c

@@ -0,0 +1,17 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Lijian Zhao <lijian.zhao@intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <arch/acpi.h>
+
+void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
+{
+}

src/mainboard/intel/apollolake_rvp/dsdt.asl

@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Lijian Zhao <lijian.zhao@intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,		/* DSDT revision: ACPI v2.0 */
+	"COREv4",	/* OEM id */
+	"COREBOOT",	/* OEM table id */
+	0x20110725	/* OEM revision */
+)
+{
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+			Name (_HID, EISAID ("PNP0A08"))	/* PCIe */
+		}
+	}
+
+}

src/soc/intel/apollolake/Makefile.inc

@@ -25,6 +25,8 @@ romstage-y += memmap.c
 romstage-y += mmap_boot.c
 
 smm-y += placeholders.c
+
+ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
 ramstage-y += cpu.c
 ramstage-y += chip.c
 ramstage-y += placeholders.c

src/soc/intel/apollolake/acpi.c

@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Lijian Zhao <lijian.zhao@intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <arch/acpi.h>
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+	return 0;
+}
+unsigned long acpi_fill_madt(unsigned long current)
+{
+	return 0;
+}