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soc/intel/denverton_ns: re-factor HSIO configuration 

The main goal is to allow configuring the HSIO lines from the mainboard code.
Also share the code for both romstage and ramstage.
Remove explicit dependency on the harcuvar mainboard.

Change-Id: Iec65472207309eae878d14eef5bc644b80fdbb1d
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/22309
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Julien Viard de Galbert 2017-11-06 13:19:58 +01:00 committed by Patrick Georgi
parent 6a81184058
commit f528195bdf
4 changed files with 14 additions and 27 deletions
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15
src/soc/intel/denverton_ns/chip.c
View File

@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2015 - 2017 Intel Corp.
* Copyright (C) 2017 Online SAS.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -31,8 +32,6 @@
#include <soc/ramstage.h>
#include <soc/fiamux.h>
#include <spi-generic.h>
#include <hsio.h>
#include <harcuvar_boardid.h>
static void pci_domain_set_resources(device_t dev)
{
@ -74,7 +73,6 @@ static void soc_silicon_init_params(FSPS_UPD *silupd)
{
size_t num;
uint16_t supported_hsio_lanes;
uint8_t boardid = board_id();
BL_HSIO_INFORMATION *hsio_config;
BL_FIA_MUX_CONFIG_HOB *fiamux_hob_data = get_fiamux_hob_data();
@ -82,16 +80,7 @@ static void soc_silicon_init_params(FSPS_UPD *silupd)
supported_hsio_lanes =
(uint16_t)fiamux_hob_data->FiaMuxConfig.SkuNumLanesAllowed;
switch (boardid) {
case BoardIdHarcuvar:
num = ARRAY_SIZE(harcuvar_hsio_config);
hsio_config = (BL_HSIO_INFORMATION *)harcuvar_hsio_config;
break;
default:
num = 0;
hsio_config = NULL;
break;
}
num = mainboard_get_hsio_config(&hsio_config);
if (get_fiamux_hsio_info(supported_hsio_lanes, num, &hsio_config))
die("HSIO Configuration is invalid, please correct it!");

7
src/soc/intel/denverton_ns/fiamux.c
View File

@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2014 - 2017 Intel Corporation
* Copyright (C) 2017 Online SAS
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -138,3 +139,9 @@ BL_FIA_MUX_CONFIG_HOB *get_fiamux_hob_data(void)
return fiamux_hob_data;
}
__attribute__((weak)) size_t mainboard_get_hsio_config(BL_HSIO_INFORMATION **p_hsio_config)
{
*p_hsio_config = NULL;
return 0;
}

3
src/soc/intel/denverton_ns/include/soc/fiamux.h
View File

@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2017 Intel Corporation.
* Copyright (C) 2017 Online SAS.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -24,4 +25,6 @@ int get_fiamux_hsio_info(uint16_t num_of_lanes, size_t num_of_entry,
BL_FIA_MUX_CONFIG_HOB *get_fiamux_hob_data(void);
void print_fiamux_config_hob(BL_FIA_MUX_CONFIG_HOB *fiamux_hob_data);
size_t mainboard_get_hsio_config(BL_HSIO_INFORMATION **p_hsio_config);
#endif // _MAINBOARD_HARCUVAR_FIAMUX_H

16
src/soc/intel/denverton_ns/romstage.c
View File

@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2016 - 2017 Intel Corp.
* Copyright (C) 2017 Online SAS.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -16,8 +17,6 @@
#include <cbmem.h>
#include <console/console.h>
#include <cpu/x86/mtrr.h>
#include <harcuvar_boardid.h>
#include <hsio.h>
#include <reset.h>
#include <soc/fiamux.h>
#include <soc/iomap.h>
@ -237,7 +236,6 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg)
FSPM_UPD *mupd = container_of(m_cfg, FSPM_UPD, FspmConfig);
size_t num;
uint16_t supported_hsio_lanes;
uint8_t boardid = board_id();
BL_HSIO_INFORMATION *hsio_config;
/* Set the parameters for MemoryInit */
@ -250,17 +248,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg)
/* Assume the validating silicon has max lanes. */
supported_hsio_lanes = BL_ME_FIA_MUX_LANE_NUM_MAX;
switch (boardid) {
case BoardIdHarcuvar:
num = ARRAY_SIZE(harcuvar_hsio_config);
hsio_config =
(BL_HSIO_INFORMATION *)harcuvar_hsio_config;
break;
default:
num = 0;
hsio_config = NULL;
break;
}
num = mainboard_get_hsio_config(&hsio_config);
if (get_fiamux_hsio_info(supported_hsio_lanes, num,
&hsio_config))