mainboard/asus: Add F2A85-M LE variant to F2A85-M.
The F2A85-M LE has less DRAM slots and needs different settings. Additionally, the audio codec verb table is different. Change-Id: I0e13c91fc924f4f9eac534fd13d57830654dd0aa Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: http://review.coreboot.org/7356 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
This commit is contained in:
Tobias Diedrich
Rudolf Marek
parent
01c3f1fa64
commit
f52beee059
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@ -31,6 +31,8 @@ config BOARD_ASUS_A8V_E_DELUXE
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bool "A8V-E Deluxe"
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config BOARD_ASUS_F2A85_M
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bool "F2A85-M"
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config BOARD_ASUS_F2A85_M_LE
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bool "F2A85-M LE"
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config BOARD_ASUS_K8V_X
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bool "K8V-X"
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config BOARD_ASUS_M2N_E
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@ -72,6 +74,7 @@ source "src/mainboard/asus/a8n_sli/Kconfig"
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source "src/mainboard/asus/a8v-e_se/Kconfig"
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source "src/mainboard/asus/a8v-e_deluxe/Kconfig"
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source "src/mainboard/asus/f2a85-m/Kconfig"
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source "src/mainboard/asus/f2a85-m_le/Kconfig"
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source "src/mainboard/asus/k8v-x/Kconfig"
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source "src/mainboard/asus/m2n-e/Kconfig"
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source "src/mainboard/asus/m2v/Kconfig"
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@ -0,0 +1,111 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "AGESA.h"
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#include <northbridge/amd/agesa/BiosCallOuts.h>
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#include "OptionsIds.h"
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#include <cbfs.h>
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#include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h>
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#include <stdlib.h>
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static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr);
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const BIOS_CALLOUT_STRUCT BiosCallouts[] =
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{
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{AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer },
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{AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer },
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{AGESA_LOCATE_BUFFER, agesa_LocateBuffer },
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{AGESA_DO_RESET, agesa_Reset },
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{AGESA_READ_SPD, agesa_ReadSpd },
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{AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
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{AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
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{AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },
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{AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
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{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
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{AGESA_FCH_OEM_CALLOUT, Fch_Oem_config },
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{AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage }
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};
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const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
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/**
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* ASUS F2A85-M board ALC887-VD Verb Table
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*
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* Copied from `/sys/class/sound/hwC1D0/init_pin_configs` when running
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* the vendor BIOS.
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*/
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const CODEC_ENTRY f2a85_m_alc887_VerbTbl[] = {
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{0x11, 0x99430140},
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{0x12, 0x411111f0},
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{0x14, 0x01014010},
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{0x15, 0x411111f0},
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{0x16, 0x411111f0},
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{0x17, 0x411111f0},
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{0x18, 0x01a19850},
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{0x19, 0x02a19c60},
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{0x1a, 0x0181305f},
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{0x1b, 0x02214c20},
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{0x1c, 0x411111f0},
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{0x1d, 0x4004c601},
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{0x1e, 0x01456130},
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{0x1f, 0x411111f0},
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{0xff, 0xffffffff}
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};
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static const CODEC_TBL_LIST CodecTableList[] =
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{
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{0x10ec0887, (CODEC_ENTRY*)&f2a85_m_alc887_VerbTbl[0]},
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{(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL}
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};
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/**
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* Fch Oem setting callback
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*
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* Configure platform specific Hudson device,
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* such Azalia, SATA, GEC, IMC etc.
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*/
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static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr)
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{
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AMD_CONFIG_PARAMS *StdHeader = ConfigPtr;
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if (StdHeader->Func == AMD_INIT_RESET) {
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FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData;
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printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
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FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE);
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FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
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FchParams_reset->FchReset.Xhci1Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
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} else if (StdHeader->Func == AMD_INIT_ENV) {
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FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData;
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printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
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/* Azalia Controller OEM Codec Table Pointer */
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FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]);
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/* Azalia Controller Front Panel OEM Table Pointer */
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FchParams_env->Imc.ImcEnable = FALSE;
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FchParams_env->Hwm.HwMonitorEnable = FALSE;
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FchParams_env->Hwm.HwmFchtsiAutoPoll = FALSE;/* 1 enable, 0 disable TSI Auto Polling */
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/* XHCI configuration */
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FchParams_env->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
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FchParams_env->Usb.Xhci1Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
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}
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printk(BIOS_DEBUG, "Done\n");
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return AGESA_SUCCESS;
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}
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@ -0,0 +1,99 @@
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#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2012 Advanced Micro Devices, Inc.
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# Copyright (C) 2012 Rudolf Marek <r.marek@assembler.cz>
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#
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if BOARD_ASUS_F2A85_M_LE
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select CPU_AMD_AGESA_FAMILY15_TN
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select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
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select SOUTHBRIDGE_AMD_AGESA_HUDSON
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select HAVE_OPTION_TABLE
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select HAVE_PIRQ_TABLE
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select HAVE_MP_TABLE
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select SUPERIO_ITE_IT8728F
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select BOARD_ROMSIZE_KB_8192
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select GFXUMA
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select HUDSON_DISABLE_IMC
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select HUDSON_NOT_LEGACY_FREE
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choice
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prompt "DDR3 memory voltage"
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default BOARD_ASUS_F2A85_M_LE_DDR3_VOLT_150
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config BOARD_ASUS_F2A85_M_LE_DDR3_VOLT_135
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bool "1.35V"
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help
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Set DRR3 memory voltage to 1.35V
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config BOARD_ASUS_F2A85_M_LE_DDR3_VOLT_150
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bool "1.50V"
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help
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Set DRR3 memory voltage to 1.50V
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config BOARD_ASUS_F2A85_M_LE_DDR3_VOLT_165
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bool "1.65V"
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help
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Set DRR3 memory voltage to 1.65V
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endchoice
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config BOARD_ASUS_F2A85_M_DDR3_VOLT_VAL
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hex
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default 0x9e if BOARD_ASUS_F2A85_M_LE_DDR3_VOLT_135
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default 0x0 if BOARD_ASUS_F2A85_M_LE_DDR3_VOLT_150
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default 0x1e if BOARD_ASUS_F2A85_M_LE_DDR3_VOLT_165
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config MAINBOARD_DIR
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string
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default asus/f2a85-m_le
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config MAINBOARD_PART_NUMBER
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string
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default "F2A85-M_LE"
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config HW_MEM_HOLE_SIZEK
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hex
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default 0x200000
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config MAX_CPUS
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int
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default 4
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config HW_MEM_HOLE_SIZE_AUTO_INC
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bool
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default n
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config IRQ_SLOT_COUNT
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int
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default 11
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config ONBOARD_VGA_IS_PRIMARY
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bool
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default y
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config VGA_BIOS_ID
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string
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default "1002,9901"
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config VGA_BIOS_FILE
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string
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default "pci1002,9901.rom"
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endif # BOARD_ASUS_F2A85_M_LE
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@ -0,0 +1,28 @@
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#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2012 Advanced Micro Devices, Inc.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#
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romstage-y += buildOpts.c
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romstage-y += agesawrapper.c
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romstage-y += BiosCallOuts.c
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romstage-y += PlatformGnbPcie.c
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ramstage-y += buildOpts.c
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ramstage-y += agesawrapper.c
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ramstage-y += BiosCallOuts.c
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ramstage-y += PlatformGnbPcie.c
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@ -0,0 +1 @@
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#include "../f2a85-m/OptionsIds.h"
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@ -0,0 +1 @@
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#include "../f2a85-m/PlatformGnbPcie.c"
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@ -0,0 +1 @@
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#include "../f2a85-m/PlatformGnbPcieComplex.h"
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@ -0,0 +1 @@
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#include "../../f2a85-m/acpi/AmdImc.asl"
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@ -0,0 +1 @@
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#include "../../f2a85-m/acpi/cpstate.asl"
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@ -0,0 +1 @@
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#include "../../f2a85-m/acpi/gpe.asl"
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@ -0,0 +1 @@
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#include "../../f2a85-m/acpi/mainboard.asl"
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@ -0,0 +1 @@
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#include "../../f2a85-m/acpi/routing.asl"
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@ -0,0 +1 @@
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#include "../../f2a85-m/acpi/sata.asl"
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@ -0,0 +1 @@
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#include "../../f2a85-m/acpi/si.asl"
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@ -0,0 +1 @@
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#include "../../f2a85-m/acpi/sleep.asl"
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@ -0,0 +1 @@
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#include "../../f2a85-m/acpi/superio.asl"
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@ -0,0 +1 @@
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#include "../../f2a85-m/acpi/thermal.asl"
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@ -0,0 +1 @@
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include "../../f2a85-m/acpi/usb_oc.asl"
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@ -0,0 +1 @@
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#include "../f2a85-m/acpi_tables.c"
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@ -0,0 +1 @@
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#include "../f2a85-m/agesawrapper.c"
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@ -0,0 +1 @@
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#include "../f2a85-m/agesawrapper.h"
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@ -0,0 +1,6 @@
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Category: desktop
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Board URL: http://www.asus.com/Motherboards/F2A85M_LE/
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ROM package: DIP8
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ROM protocol: [http://www.winbond-usa.com/hq/enu/ProductAndSales/ProductLines/FlashMemory/SerialFlash/W25Q64BV.htm SPI]
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ROM socketed: y
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Flashrom support: y
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@ -0,0 +1,512 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
|
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* the Free Software Foundation; version 2 of the License.
|
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*
|
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* This program is distributed in the hope that it will be useful,
|
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
|
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*
|
||||
* You should have received a copy of the GNU General Public License
|
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* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/**
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* @file
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*
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* AMD User options selection for a Brazos platform solution system
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*
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* This file is placed in the user's platform directory and contains the
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* build option selections desired for that platform.
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*
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* For Information about this file, see @ref platforminstall.
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*
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* @xrefitem bom "File Content Label" "Release Content"
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* @e project: AGESA
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* @e sub-project: Core
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* @e \$Revision: 23714 $ @e \$Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $
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*/
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#include <stdlib.h>
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#include <vendorcode/amd/agesa/f15tn/AGESA.h>
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/* Include the files that instantiate the configuration definitions. */
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#include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h>
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#include <vendorcode/amd/agesa/f15tn/Include/CommonReturns.h>
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#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h>
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#include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h>
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#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
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/* the next two headers depend on heapManager.h */
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#include <vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.h>
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#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.h>
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/* These tables are optional and may be used to adjust memory timing settings */
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#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h>
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#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h>
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#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
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/* Select the cpu family. */
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#define INSTALL_FAMILY_10_SUPPORT FALSE
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#define INSTALL_FAMILY_12_SUPPORT FALSE
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#define INSTALL_FAMILY_14_SUPPORT FALSE
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#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
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/* Select the cpu socket type. */
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#define INSTALL_G34_SOCKET_SUPPORT FALSE
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#define INSTALL_C32_SOCKET_SUPPORT FALSE
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#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
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#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
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#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
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#define INSTALL_FS1_SOCKET_SUPPORT FALSE
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#define INSTALL_FM1_SOCKET_SUPPORT FALSE
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#define INSTALL_FP2_SOCKET_SUPPORT FALSE
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#define INSTALL_FT1_SOCKET_SUPPORT FALSE
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#define INSTALL_AM3_SOCKET_SUPPORT FALSE
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#define INSTALL_FM2_SOCKET_SUPPORT TRUE
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//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE
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#define BLDOPT_REMOVE_SODIMMS_SUPPORT TRUE
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#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
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#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE
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#define BLDOPT_REMOVE_ECC_SUPPORT TRUE
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//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE
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//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE
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#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
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#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE
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#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
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//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE
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#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
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//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE
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#define BLDOPT_REMOVE_SRAT FALSE //TRUE
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#define BLDOPT_REMOVE_SLIT FALSE //TRUE
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#define BLDOPT_REMOVE_WHEA FALSE //TRUE
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#define BLDOPT_REMOVE_CRAT TRUE
|
||||
#define BLDOPT_REMOVE_DMI TRUE
|
||||
//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE
|
||||
//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE
|
||||
//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE
|
||||
//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE
|
||||
//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE
|
||||
//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE
|
||||
|
||||
//This element selects whether P-States should be forced to be independent,
|
||||
// as reported by the ACPI _PSD object. For single-link processors,
|
||||
// setting TRUE for OS to support this feature.
|
||||
|
||||
//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE
|
||||
|
||||
#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
|
||||
#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
|
||||
/* Build configuration values here.
|
||||
*/
|
||||
#define BLDCFG_VRM_CURRENT_LIMIT 90000
|
||||
#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0
|
||||
#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 0
|
||||
#define BLDCFG_PLAT_NUM_IO_APICS 3
|
||||
#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
|
||||
#define BLDCFG_MEM_INIT_PSTATE 0
|
||||
|
||||
#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
|
||||
|
||||
#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY
|
||||
#define BLDCFG_MEMORY_MODE_UNGANGED TRUE
|
||||
#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE
|
||||
#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
|
||||
#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE
|
||||
#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE
|
||||
#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE
|
||||
#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
|
||||
#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
|
||||
#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE
|
||||
#define BLDCFG_MEMORY_POWER_DOWN TRUE
|
||||
#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT
|
||||
#define BLDCFG_ONLINE_SPARE FALSE
|
||||
#define BLDCFG_BANK_SWIZZLE TRUE
|
||||
#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
|
||||
#define BLDCFG_MEMORY_CLOCK_SELECT DDR1600_FREQUENCY
|
||||
#define BLDCFG_DQS_TRAINING_CONTROL TRUE
|
||||
#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE
|
||||
#define BLDCFG_USE_BURST_MODE FALSE
|
||||
#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE
|
||||
#define BLDCFG_ENABLE_ECC_FEATURE FALSE
|
||||
#define BLDCFG_ECC_REDIRECTION FALSE
|
||||
#define BLDCFG_SCRUB_DRAM_RATE 0
|
||||
#define BLDCFG_SCRUB_L2_RATE 0
|
||||
#define BLDCFG_SCRUB_L3_RATE 0
|
||||
#define BLDCFG_SCRUB_IC_RATE 0
|
||||
#define BLDCFG_SCRUB_DC_RATE 0
|
||||
#define BLDCFG_ECC_SYMBOL_SIZE 4
|
||||
#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000
|
||||
#define BLDCFG_ECC_SYNC_FLOOD FALSE
|
||||
#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
|
||||
#define BLDCFG_1GB_ALIGN FALSE
|
||||
#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
|
||||
#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default value 0.36%
|
||||
#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770
|
||||
|
||||
#define BLDOPT_REMOVE_ALIB FALSE
|
||||
#define BLDCFG_PLATFORM_CPB_MODE CpbModeDisabled
|
||||
#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P'
|
||||
#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0'
|
||||
#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6
|
||||
|
||||
#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200
|
||||
#define BLDCFG_CFG_ABM_SUPPORT 0
|
||||
|
||||
//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770
|
||||
|
||||
// Specify the default values for the VRM controlling the VDDNB plane.
|
||||
// If not specified, the values used for the core VRM will be applied
|
||||
//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity
|
||||
//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L
|
||||
//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime
|
||||
//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity
|
||||
//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity
|
||||
//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity
|
||||
|
||||
#define BLDCFG_VRM_NB_CURRENT_LIMIT 60000
|
||||
|
||||
#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3
|
||||
#define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3
|
||||
|
||||
#if CONFIG_GFXUMA
|
||||
#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED
|
||||
#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED
|
||||
//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/
|
||||
#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M
|
||||
#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE
|
||||
#endif
|
||||
|
||||
#define BLDCFG_IOMMU_SUPPORT FALSE
|
||||
|
||||
#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
|
||||
//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID
|
||||
//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID
|
||||
//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID
|
||||
|
||||
/* Process the options...
|
||||
* This file include MUST occur AFTER the user option selection settings
|
||||
*/
|
||||
#define AGESA_ENTRY_INIT_RESET TRUE
|
||||
#define AGESA_ENTRY_INIT_RECOVERY FALSE
|
||||
#define AGESA_ENTRY_INIT_EARLY TRUE
|
||||
#define AGESA_ENTRY_INIT_POST TRUE
|
||||
#define AGESA_ENTRY_INIT_ENV TRUE
|
||||
#define AGESA_ENTRY_INIT_MID TRUE
|
||||
#define AGESA_ENTRY_INIT_LATE TRUE
|
||||
#define AGESA_ENTRY_INIT_S3SAVE TRUE
|
||||
#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE
|
||||
#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
|
||||
#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
|
||||
/*
|
||||
* Customized OEM build configurations for FCH component
|
||||
*/
|
||||
// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00
|
||||
// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20
|
||||
// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00
|
||||
// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400
|
||||
// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404
|
||||
// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408
|
||||
// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410
|
||||
// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420
|
||||
// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000
|
||||
// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000
|
||||
// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000
|
||||
// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0
|
||||
// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00
|
||||
// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000
|
||||
// #define BLDCFG_AZALIA_SSID 0x780D1022
|
||||
// #define BLDCFG_SMBUS_SSID 0x780B1022
|
||||
// #define BLDCFG_IDE_SSID 0x780C1022
|
||||
// #define BLDCFG_SATA_AHCI_SSID 0x78011022
|
||||
// #define BLDCFG_SATA_IDE_SSID 0x78001022
|
||||
// #define BLDCFG_SATA_RAID5_SSID 0x78031022
|
||||
// #define BLDCFG_SATA_RAID_SSID 0x78021022
|
||||
// #define BLDCFG_EHCI_SSID 0x78081022
|
||||
// #define BLDCFG_OHCI_SSID 0x78071022
|
||||
// #define BLDCFG_LPC_SSID 0x780E1022
|
||||
// #define BLDCFG_SD_SSID 0x78061022
|
||||
// #define BLDCFG_XHCI_SSID 0x78121022
|
||||
// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE
|
||||
// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
|
||||
// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4
|
||||
// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE
|
||||
// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE
|
||||
// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE
|
||||
// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE
|
||||
// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE
|
||||
// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE
|
||||
// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE
|
||||
// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
|
||||
|
||||
CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
|
||||
{
|
||||
{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
|
||||
{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
|
||||
{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
|
||||
{ AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 },
|
||||
{ AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 },
|
||||
{ AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 },
|
||||
{ AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 },
|
||||
{ AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 },
|
||||
{ AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 },
|
||||
{ AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 },
|
||||
{ AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 },
|
||||
{ CPU_LIST_TERMINAL }
|
||||
};
|
||||
|
||||
#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList
|
||||
|
||||
// This is the delivery package title, "BrazosPI"
|
||||
// This string MUST be exactly 8 characters long
|
||||
#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
|
||||
|
||||
// This is the release version number of the AGESA component
|
||||
// This string MUST be exactly 12 characters long
|
||||
#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
|
||||
|
||||
/* MEMORY_BUS_SPEED */
|
||||
#define DDR400_FREQUENCY 200 ///< DDR 400
|
||||
#define DDR533_FREQUENCY 266 ///< DDR 533
|
||||
#define DDR667_FREQUENCY 333 ///< DDR 667
|
||||
#define DDR800_FREQUENCY 400 ///< DDR 800
|
||||
#define DDR1066_FREQUENCY 533 ///< DDR 1066
|
||||
#define DDR1333_FREQUENCY 667 ///< DDR 1333
|
||||
#define DDR1600_FREQUENCY 800 ///< DDR 1600
|
||||
#define DDR1866_FREQUENCY 933 ///< DDR 1866
|
||||
#define DDR2100_FREQUENCY 1050 ///< DDR 2100
|
||||
#define DDR2133_FREQUENCY 1066 ///< DDR 2133
|
||||
#define DDR2400_FREQUENCY 1200 ///< DDR 2400
|
||||
#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
|
||||
|
||||
/* QUANDRANK_TYPE*/
|
||||
#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
|
||||
#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
|
||||
|
||||
/* USER_MEMORY_TIMING_MODE */
|
||||
#define TIMING_MODE_AUTO 0 ///< Use best rate possible
|
||||
#define TIMING_MODE_LIMITED 1 ///< Set user top limit
|
||||
#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
|
||||
|
||||
/* POWER_DOWN_MODE */
|
||||
#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
|
||||
#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
|
||||
|
||||
/*
|
||||
* Agesa optional capabilities selection.
|
||||
* Uncomment and mark FALSE those features you wish to include in the build.
|
||||
* Comment out or mark TRUE those features you want to REMOVE from the build.
|
||||
*/
|
||||
|
||||
#define DFLT_SMBUS0_BASE_ADDRESS 0xB00
|
||||
#define DFLT_SMBUS1_BASE_ADDRESS 0xB20
|
||||
/* The AGESA likes to enable 512 bytes region on this base for LPC bus */
|
||||
#define DFLT_SIO_PME_BASE_ADDRESS 0xE00
|
||||
#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800
|
||||
#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804
|
||||
#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808
|
||||
#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810
|
||||
#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820
|
||||
#define DFLT_SPI_BASE_ADDRESS 0xFEC10000
|
||||
#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0
|
||||
#define DFLT_HPET_BASE_ADDRESS 0xFED00000
|
||||
#define DFLT_SMI_CMD_PORT 0xB0
|
||||
#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00
|
||||
#define DFLT_GEC_BASE_ADDRESS 0xFED61000
|
||||
#define DFLT_AZALIA_SSID 0x780D1022
|
||||
#define DFLT_SMBUS_SSID 0x780B1022
|
||||
#define DFLT_IDE_SSID 0x780C1022
|
||||
#define DFLT_SATA_AHCI_SSID 0x78011022
|
||||
#define DFLT_SATA_IDE_SSID 0x78001022
|
||||
#define DFLT_SATA_RAID5_SSID 0x78031022
|
||||
#define DFLT_SATA_RAID_SSID 0x78021022
|
||||
#define DFLT_EHCI_SSID 0x78081022
|
||||
#define DFLT_OHCI_SSID 0x78071022
|
||||
#define DFLT_LPC_SSID 0x780E1022
|
||||
#define DFLT_SD_SSID 0x78061022
|
||||
#define DFLT_XHCI_SSID 0x78121022
|
||||
#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE
|
||||
#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
|
||||
#define DFLT_FCH_GPP_LINK_CONFIG PortA1B1C1D1
|
||||
#define DFLT_FCH_GPP_PORT0_PRESENT TRUE
|
||||
#define DFLT_FCH_GPP_PORT1_PRESENT TRUE
|
||||
#define DFLT_FCH_GPP_PORT2_PRESENT FALSE
|
||||
#define DFLT_FCH_GPP_PORT3_PRESENT FALSE
|
||||
#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE
|
||||
#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
|
||||
#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
|
||||
#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
|
||||
//#define BLDCFG_IR_PIN_CONTROL 0x33
|
||||
//#define FCH_NO_XHCI_SUPPORT FALSE
|
||||
GPIO_CONTROL f2a85_m_gpio[] = {
|
||||
// {183, Function1, PullUpB},
|
||||
{-1}
|
||||
};
|
||||
#define BLDCFG_FCH_GPIO_CONTROL_LIST (&f2a85_m_gpio[0])
|
||||
|
||||
// The following definitions specify the default values for various parameters in which there are
|
||||
// no clearly defined defaults to be used in the common file. The values below are based on product
|
||||
// and BKDG content, please consult the AGESA Memory team for consultation.
|
||||
#define DFLT_SCRUB_DRAM_RATE (0)
|
||||
#define DFLT_SCRUB_L2_RATE (0)
|
||||
#define DFLT_SCRUB_L3_RATE (0)
|
||||
#define DFLT_SCRUB_IC_RATE (0)
|
||||
#define DFLT_SCRUB_DC_RATE (0)
|
||||
#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
|
||||
#define DFLT_VRM_SLEW_RATE (5000)
|
||||
|
||||
/* Moving this include up will break AGESA. */
|
||||
#include <vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h>
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* CUSTOMER OVERIDES MEMORY TABLE
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*
|
||||
* Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
|
||||
* (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
|
||||
* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
|
||||
* use its default conservative settings.
|
||||
*/
|
||||
CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
|
||||
//
|
||||
// The following macros are supported (use comma to separate macros):
|
||||
//
|
||||
// MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
|
||||
// The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
|
||||
// AGESA will base on this value to disable unused MemClk to save power.
|
||||
// Example:
|
||||
// BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
|
||||
// Bit AM3/S1g3 pin name
|
||||
// 0 M[B,A]_CLK_H/L[0]
|
||||
// 1 M[B,A]_CLK_H/L[1]
|
||||
// 2 M[B,A]_CLK_H/L[2]
|
||||
// 3 M[B,A]_CLK_H/L[3]
|
||||
// 4 M[B,A]_CLK_H/L[4]
|
||||
// 5 M[B,A]_CLK_H/L[5]
|
||||
// 6 M[B,A]_CLK_H/L[6]
|
||||
// 7 M[B,A]_CLK_H/L[7]
|
||||
// And platform has the following routing:
|
||||
// CS0 M[B,A]_CLK_H/L[4]
|
||||
// CS1 M[B,A]_CLK_H/L[2]
|
||||
// CS2 M[B,A]_CLK_H/L[3]
|
||||
// CS3 M[B,A]_CLK_H/L[5]
|
||||
// Then platform can specify the following macro:
|
||||
// MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
|
||||
//
|
||||
// CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
|
||||
// The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
|
||||
// AGESA will base on this value to tristate unused CKE to save power.
|
||||
//
|
||||
// ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
|
||||
// The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
|
||||
// AGESA will base on this value to tristate unused ODT pins to save power.
|
||||
//
|
||||
// CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
|
||||
// The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
|
||||
// AGESA will base on this value to tristate unused Chip select to save power.
|
||||
//
|
||||
// NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
|
||||
// Specifies the number of DIMM slots per channel.
|
||||
//
|
||||
// NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
|
||||
// Specifies the number of Chip selects per channel.
|
||||
//
|
||||
// NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
|
||||
// Specifies the number of channels per socket.
|
||||
//
|
||||
// OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
|
||||
// Specifies DDR bus speed of channel ChannelID on socket SocketID.
|
||||
//
|
||||
// DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
|
||||
// Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
|
||||
//
|
||||
// WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
|
||||
// Byte6Seed, Byte7Seed, ByteEccSeed)
|
||||
// Specifies the write leveling seed for a channel of a socket.
|
||||
//
|
||||
// HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
|
||||
// Byte6Seed, Byte7Seed, ByteEccSeed)
|
||||
// Speicifes the HW RXEN training seed for a channel of a socket
|
||||
//
|
||||
|
||||
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
|
||||
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
|
||||
|
||||
/*
|
||||
TODO: is this OK for DDR3 socket FM2?
|
||||
MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
|
||||
CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A),
|
||||
ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00),
|
||||
CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
|
||||
*/
|
||||
PSO_END
|
||||
};
|
||||
|
||||
// Customer table
|
||||
UINT8 AGESA_MEM_TABLE_TN[][sizeof (MEM_TABLE_ALIAS)] =
|
||||
{
|
||||
// Hardcoded Memory Training Values
|
||||
|
||||
// The following macro should be used to override training values for your platform
|
||||
//
|
||||
// DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20),
|
||||
//
|
||||
// NOTE:
|
||||
// The following training hardcode values are example values that were taken from a tilapia motherboard
|
||||
// with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in
|
||||
// the table and replace the byte lane values with your own.
|
||||
//
|
||||
// ------------------ BYTE LANES ----------------------
|
||||
// BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC
|
||||
// Write Data Timing
|
||||
// DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0
|
||||
// DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1
|
||||
// DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM0, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x27, 0x2B, 0x3B, 0x3B, 0x3E, 0x3E, 0x30),// DCT1, DIMM0
|
||||
// DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM1, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x1C, 0x0B, 0x17, 0x1A, 0x1D, 0x1C, 0x10),// DCT1, DIMM1
|
||||
|
||||
// DQS Receiver Enable
|
||||
// DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0
|
||||
// DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM1, BFRcvEnDly, MTOverride, 0x7C, 0x7D, 0x7E, 0x81, 0x88, 0x8F, 0x96, 0x9F, 0x84),// DCT0, DIMM1
|
||||
// DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT1, DIMM0
|
||||
// DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM1, BFRcvEnDly, MTOverride, 0x1C, 0x1D, 0x1E, 0x01, 0x08, 0x0F, 0x16, 0x1F, 0x04),// DCT1, DIMM1
|
||||
|
||||
// Write DQS Delays
|
||||
// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDqsDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0
|
||||
// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDqsDly, MTOverride, 0x06, 0x0D, 0x12, 0x1A, 0x25, 0x28, 0x2C, 0x2C, 0x44),// DCT0, DIMM1
|
||||
// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFWrDqsDly, MTOverride, 0x07, 0x0E, 0x14, 0x1B, 0x24, 0x29, 0x2B, 0x2C, 0x1F),// DCT1, DIMM0
|
||||
// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFWrDqsDly, MTOverride, 0x07, 0x0C, 0x14, 0x19, 0x25, 0x28, 0x2B, 0x2B, 0x1A),// DCT1, DIMM1
|
||||
|
||||
// Read DQS Delays
|
||||
// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x0E, 0x10),// DCT0, DIMM0
|
||||
// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT0, DIMM1
|
||||
// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM0
|
||||
// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1
|
||||
//--------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
// TABLE END
|
||||
NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table
|
||||
};
|
||||
UINT8 SizeOfTableTN = ARRAY_SIZE(AGESA_MEM_TABLE_TN);
|
||||
|
||||
/* ***************************************************************************
|
||||
* Optional User code to be included into the AGESA build
|
||||
* These may be 32-bit call-out routines...
|
||||
*/
|
||||
//AGESA_STATUS
|
||||
//AgesaReadSpd (
|
||||
// IN UINTN FcnData,
|
||||
// IN OUT AGESA_READ_SPD_PARAMS *ReadSpd
|
||||
// )
|
||||
//{
|
||||
// /* platform code to read an SPD... */
|
||||
// return Status;
|
||||
//}
|
||||
|
|
@ -0,0 +1,114 @@
|
|||
#*****************************************************************************
|
||||
#
|
||||
# This file is part of the coreboot project.
|
||||
#
|
||||
# Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; version 2 of the License.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
#*****************************************************************************
|
||||
|
||||
entries
|
||||
|
||||
#start-bit length config config-ID name
|
||||
#0 8 r 0 seconds
|
||||
#8 8 r 0 alarm_seconds
|
||||
#16 8 r 0 minutes
|
||||
#24 8 r 0 alarm_minutes
|
||||
#32 8 r 0 hours
|
||||
#40 8 r 0 alarm_hours
|
||||
#48 8 r 0 day_of_week
|
||||
#56 8 r 0 day_of_month
|
||||
#64 8 r 0 month
|
||||
#72 8 r 0 year
|
||||
#80 4 r 0 rate_select
|
||||
#84 3 r 0 REF_Clock
|
||||
#87 1 r 0 UIP
|
||||
#88 1 r 0 auto_switch_DST
|
||||
#89 1 r 0 24_hour_mode
|
||||
#90 1 r 0 binary_values_enable
|
||||
#91 1 r 0 square-wave_out_enable
|
||||
#92 1 r 0 update_finished_enable
|
||||
#93 1 r 0 alarm_interrupt_enable
|
||||
#94 1 r 0 periodic_interrupt_enable
|
||||
#95 1 r 0 disable_clock_updates
|
||||
#96 288 r 0 temporary_filler
|
||||
0 384 r 0 reserved_memory
|
||||
384 1 e 4 boot_option
|
||||
385 1 e 4 last_boot
|
||||
386 1 e 1 ECC_memory
|
||||
388 4 r 0 reboot_bits
|
||||
392 3 e 5 baud_rate
|
||||
395 1 e 1 hw_scrubber
|
||||
396 1 e 1 interleave_chip_selects
|
||||
397 2 e 8 max_mem_clock
|
||||
399 1 e 2 multi_core
|
||||
400 1 e 1 power_on_after_fail
|
||||
412 4 e 6 debug_level
|
||||
416 4 e 7 boot_first
|
||||
420 4 e 7 boot_second
|
||||
424 4 e 7 boot_third
|
||||
428 4 h 0 boot_index
|
||||
432 8 h 0 boot_countdown
|
||||
440 4 e 9 slow_cpu
|
||||
444 1 e 1 nmi
|
||||
445 1 e 1 iommu
|
||||
728 256 h 0 user_data
|
||||
984 16 h 0 check_sum
|
||||
# Reserve the extended AMD configuration registers
|
||||
1000 24 r 0 amd_reserved
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
5 0 115200
|
||||
5 1 57600
|
||||
5 2 38400
|
||||
5 3 19200
|
||||
5 4 9600
|
||||
5 5 4800
|
||||
5 6 2400
|
||||
5 7 1200
|
||||
6 6 Notice
|
||||
6 7 Info
|
||||
6 8 Debug
|
||||
6 9 Spew
|
||||
7 0 Network
|
||||
7 1 HDD
|
||||
7 2 Floppy
|
||||
7 8 Fallback_Network
|
||||
7 9 Fallback_HDD
|
||||
7 10 Fallback_Floppy
|
||||
#7 3 ROM
|
||||
8 0 400Mhz
|
||||
8 1 333Mhz
|
||||
8 2 266Mhz
|
||||
8 3 200Mhz
|
||||
9 0 off
|
||||
9 1 87.5%
|
||||
9 2 75.0%
|
||||
9 3 62.5%
|
||||
9 4 50.0%
|
||||
9 5 37.5%
|
||||
9 6 25.0%
|
||||
9 7 12.5%
|
||||
|
||||
checksums
|
||||
|
||||
checksum 392 983 984
|
||||
|
|
@ -0,0 +1,138 @@
|
|||
#
|
||||
# This file is part of the coreboot project.
|
||||
#
|
||||
# Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; version 2 of the License.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
#
|
||||
chip northbridge/amd/agesa/family15tn/root_complex
|
||||
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/agesa/family15tn
|
||||
device lapic 10 on end
|
||||
end
|
||||
end
|
||||
|
||||
device domain 0 on
|
||||
subsystemid 0x1022 0x1410 inherit
|
||||
chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
|
||||
|
||||
chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
|
||||
device pci 0.0 on end # Root Complex
|
||||
device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX
|
||||
device pci 1.1 on end # Internal Multimedia
|
||||
device pci 2.0 on end # PCIE SLOT0 x16 blue
|
||||
device pci 3.0 off end # unused?
|
||||
device pci 4.0 on end # PCIE 4x black
|
||||
device pci 5.0 off end # unused?
|
||||
device pci 6.0 off end # unused?
|
||||
device pci 7.0 off end # LAN
|
||||
device pci 8.0 off end # NB/SB Link P2P bridge
|
||||
end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
|
||||
|
||||
chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus
|
||||
device pci 10.0 on end # XHCI HC0
|
||||
device pci 10.1 on end # XHCI HC1
|
||||
device pci 11.0 on end # SATA
|
||||
device pci 12.0 on end # USB
|
||||
device pci 12.2 on end # USB
|
||||
device pci 13.0 on end # USB
|
||||
device pci 13.2 on end # USB
|
||||
device pci 14.0 on # SMBUS
|
||||
chip drivers/generic/generic #dimm 0
|
||||
device i2c 50 on end # 7-bit SPD address
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1
|
||||
device i2c 51 on end # 7-bit SPD address
|
||||
end
|
||||
end # SM
|
||||
device pci 14.1 off end # IDE 0x439c
|
||||
device pci 14.2 on end # HDA 0x4383
|
||||
device pci 14.3 on # LPC 0x439d
|
||||
chip superio/ite/it8728f
|
||||
register hwm_ctl_register = "0xc0"
|
||||
register hwm_main_ctl_register = "0x33"
|
||||
register hwm_adc_temp_chan_en_reg = "0x38"
|
||||
register hwm_fan1_ctl_pwm = "0x00"
|
||||
register hwm_fan2_ctl_pwm = "0x00"
|
||||
register hwm_fan3_ctl_pwm = "0x00"
|
||||
|
||||
device pnp 2e.0 off # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.1 on # Com1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.2 off # Com2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.3 off # Parallel Port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 2e.4 on # Env Controller
|
||||
io 0x60 = 0x290
|
||||
io 0x62 = 0x220
|
||||
irq 0x70 = 0
|
||||
end
|
||||
device pnp 2e.5 on # Keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
end
|
||||
device pnp 2e.6 off # Mouse
|
||||
irq 0x70 = 12
|
||||
end
|
||||
device pnp 2e.7 on # GPIO
|
||||
io 0x60 = 0x228 #SMI
|
||||
io 0x62 = 0x300 #Simple I/O
|
||||
io 0x64 = 0x238 #Phony resource IT8603E does not have it
|
||||
irq 0x70 = 0
|
||||
end
|
||||
device pnp 2e.a off end # CIR
|
||||
end #superio/ite/it8728f
|
||||
end #device pci 14.3 # LPC
|
||||
device pci 14.4 on end # PCI 0x4384
|
||||
device pci 14.5 on end # USB 2
|
||||
device pci 14.6 off end # Gec
|
||||
device pci 14.7 off end # SD
|
||||
device pci 15.0 on end # PCIe 0 - onboard PCIe 1x
|
||||
device pci 15.1 on end # PCIe 1 onboard gigabit
|
||||
device pci 15.2 off end # unused
|
||||
device pci 15.3 off end # unused
|
||||
|
||||
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
|
||||
register "gpp_configuration" = "4"
|
||||
end #chip southbridge/amd/hudson
|
||||
|
||||
device pci 18.0 on end
|
||||
device pci 18.1 on end
|
||||
device pci 18.2 on end
|
||||
device pci 18.3 on end
|
||||
device pci 18.4 on end
|
||||
device pci 18.5 on end
|
||||
|
||||
register "spdAddrLookup" = "
|
||||
{
|
||||
{ {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
|
||||
{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
|
||||
}"
|
||||
|
||||
end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
|
||||
end #domain
|
||||
end #chip northbridge/amd/agesa/family15tn/root_complex
|
||||
|
|
@ -0,0 +1 @@
|
|||
#include "../f2a85-m/dsdt.asl"
|
||||
|
|
@ -0,0 +1 @@
|
|||
#include "../f2a85-m/irq_tables.c"
|
||||
|
|
@ -0,0 +1 @@
|
|||
#include "../f2a85-m/mainboard.c"
|
||||
|
|
@ -0,0 +1 @@
|
|||
#include <mainboard/asus/f2a85-m/mptable.c>
|
||||
|
|
@ -0,0 +1 @@
|
|||
#include "../f2a85-m/romstage.c"
|
||||
Loading…
Reference in New Issue