util/spd_tools: Encode SDRAM min cycle time (TCKMinPs)
ADL encodes CK cycle time as tCKMin whereas Sabrina encodes WCK cycle time. Encode tCKMin as per the respective advisories. BUG=None TEST=Generate the SPD and ensure that tCKMin is encoded accordingly. Minimum CAS Latency time is also impacted and is encoded accordingly. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I99ada7ead3a75befb0f934af871eecc060adcb26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
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23 11 13 0E 85 19 B5 18 00 40 00 00 0A 02 00 00
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00 00 0A 00 00 00 00 00 AA 00 90 A8 90 90 06 C0
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@ -44,7 +44,7 @@ type LP5DensityParams struct {
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}
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}
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type LP5SpeedParams struct {
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type LP5SpeedParams struct {
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TCKMinPs int
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defaultTCKMinPs int
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MaxCASLatency int
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MaxCASLatency int
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}
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}
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@ -69,6 +69,7 @@ type LP5Set struct {
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optionalFeatures byte
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optionalFeatures byte
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otherOptionalFeatures byte
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otherOptionalFeatures byte
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busWidthEncoding byte
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busWidthEncoding byte
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speedToTCKMinPs map[int]int
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}
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}
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/* ------------------------------------------------------------------------------------------ */
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/* ------------------------------------------------------------------------------------------ */
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@ -194,6 +195,19 @@ var LP5SetInfo = map[int]LP5Set{
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* Set to 0x01.
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* Set to 0x01.
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*/
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*/
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busWidthEncoding: 0x01,
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busWidthEncoding: 0x01,
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/*
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* TCKMinPs:
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* LPDDR5 has two clocks: the command/address clock (CK) and the data clock (WCK). They are
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* related by the WCK:CK ratio, which can be either 4:1 or 2:1. On ADL, 4:1 is used.
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* For ADL, the MRC expects the tCKmin to encode the CK cycle time.
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* tCKmin = 1 / CK rate
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* = 1 / (WCK rate / WCK:CK)
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* = 1 / (speed grade / 2 / WCK:CK) // "double data rate"
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*/
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speedToTCKMinPs: map[int]int{
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6400 : 1250, /* 1 / (6400 / 2 / 4) */
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5500 : 1455, /* 1 / (5500 / 2 / 4) */
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},
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},
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},
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1: {
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1: {
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SPDRevision: LP5SPDValueRevision1_1,
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SPDRevision: LP5SPDValueRevision1_1,
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@ -346,23 +360,20 @@ var LP5BankArchToSPDEncoding = map[int]LP5BankArchParams{
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/*
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/*
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* TCKMinPs:
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* TCKMinPs:
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* LPDDR5 has two clocks: the command/address clock (CK) and the data clock (WCK). They are
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* Data sheets recommend encoding the the WCK cycle time.
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* related by the WCK:CK ratio, which can be either 4:1 or 2:1. On ADL, 4:1 is used.
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* tCKmin = 1 / WCK rate
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* For ADL, the MRC expects the tCKmin to encode the CK period. This is calculated as:
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* = 1 / (speed grade / 2) // "double data rate"
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* tCKmin = 1 / CK rate
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* = 1 / (WCK rate / WCK:CK)
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* = 1 / (speed grade / 2 / WCK:CK) // "double data rate"
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*
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*
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* MaxCASLatency:
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* MaxCASLatency:
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* From Table 220 of JESD209-5B, using a 4:1 WCK:CK ratio and Set 0.
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* From Table 220 of JESD209-5B, using a 4:1 WCK:CK ratio and Set 0.
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*/
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*/
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var LP5SpeedMbpsToSPDEncoding = map[int]LP5SpeedParams{
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var LP5SpeedMbpsToSPDEncoding = map[int]LP5SpeedParams{
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6400: {
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6400: {
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TCKMinPs: 1250, /* 1 / (6400 / 2 / 4) */
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defaultTCKMinPs : 312, /* 1 / (6400 / 2) */
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MaxCASLatency: 17,
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MaxCASLatency: 17,
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},
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},
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5500: {
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5500: {
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TCKMinPs: 1455, /* 1 / (5500 / 2 / 4) */
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defaultTCKMinPs : 363, /* 1 / (5500 / 2) */
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MaxCASLatency: 15,
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MaxCASLatency: 15,
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},
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},
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}
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}
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@ -550,6 +561,21 @@ func LP5EncodeBusWidth(memAttribs *LP5MemAttributes) byte {
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return f.busWidthEncoding
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return f.busWidthEncoding
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}
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}
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func LP5GetTCKMinPs(memAttribs *LP5MemAttributes) int {
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f, ok := LP5SetInfo[LP5CurrSet]
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if ok == false || f.speedToTCKMinPs == nil {
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return LP5SpeedMbpsToSPDEncoding[memAttribs.SpeedMbps].defaultTCKMinPs
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}
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tCKMinPs, ok := f.speedToTCKMinPs[memAttribs.SpeedMbps]
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if ok == false || tCKMinPs == 0 {
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fmt.Printf("TCKMinPs not defined for speed %d(Mbps) in LP5Set %d\n", memAttribs.SpeedMbps, LP5CurrSet)
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}
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return tCKMinPs
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}
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func LP5EncodeTCKMin(memAttribs *LP5MemAttributes) byte {
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func LP5EncodeTCKMin(memAttribs *LP5MemAttributes) byte {
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return convPsToMtbByte(memAttribs.TCKMinPs)
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return convPsToMtbByte(memAttribs.TCKMinPs)
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}
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}
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@ -608,7 +634,7 @@ func LP5EncodeTRFCPBMinLsb(memAttribs *LP5MemAttributes) byte {
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func LP5UpdateTCKMin(memAttribs *LP5MemAttributes) {
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func LP5UpdateTCKMin(memAttribs *LP5MemAttributes) {
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if memAttribs.TCKMinPs == 0 {
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if memAttribs.TCKMinPs == 0 {
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memAttribs.TCKMinPs = LP5SpeedMbpsToSPDEncoding[memAttribs.SpeedMbps].TCKMinPs
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memAttribs.TCKMinPs = LP5GetTCKMinPs(memAttribs)
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}
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}
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}
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}
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