S3 code in the mainboard.
Persimmon is the demo board. Tested by Linux and Windows 7. Change-Id: I5ded942b51e63ebeb08ace0b202b4ed239b0c14c Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/624 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
This commit is contained in:
zbao
Marc Jones
parent
f72237346d
commit
f543c7b6d3
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@ -119,8 +119,10 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
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AllocParams->BufferPointer = NULL;
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AvailableHeapSize = BIOS_HEAP_SIZE - sizeof (BIOS_HEAP_MANAGER);
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BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS;
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BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS;
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BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader));
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BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr;
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printk(BIOS_SPEW, "%s BiosHeapBaseAddr: %x\n", __func__, (u32) BiosHeapBaseAddr);
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if (BiosHeapBasePtr->StartOfAllocatedNodes == 0) {
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/* First allocation */
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@ -242,11 +244,11 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
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BIOS_HEAP_MANAGER *BiosHeapBasePtr;
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AGESA_BUFFER_PARAMS *AllocParams;
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BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS;
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BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS;
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AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr;
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BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader));
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BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr;
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/* Find target node to deallocate in list of allocated nodes.
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Return AGESA_BOUNDS_CHK if the BufferHandle is not found
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*/
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@ -355,8 +357,8 @@ AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
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AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr;
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BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS;
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BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS;
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BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader));
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BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr;
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AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
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AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
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@ -23,8 +23,8 @@
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#include "Porting.h"
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#include "AGESA.h"
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#define BIOS_HEAP_START_ADDRESS 0x00010000
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#define BIOS_HEAP_SIZE 0x20000 /* 64MB */
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#define BIOS_HEAP_SIZE 0x20000
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#define BSP_STACK_BASE_ADDR 0x30000
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typedef struct _BIOS_HEAP_MANAGER {
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//UINT32 AvailableSize;
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@ -33,6 +33,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select HAVE_PIRQ_TABLE
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select HAVE_MP_TABLE
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select HAVE_MAINBOARD_RESOURCES
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select HAVE_ACPI_RESUME
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select HAVE_HARD_RESET
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select SB_HT_CHAIN_UNITID_OFFSET_ONLY
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select LIFT_BSP_APIC_ID
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@ -23,6 +23,7 @@
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#include "heapManager.h"
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#include "PlatformGnbPcieComplex.h"
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#include "Filecode.h"
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#include "BiosCallOuts.h"
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#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE
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@ -165,4 +166,3 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
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InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
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InitEarly->GnbConfig.PsppPolicy = 0;
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}
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@ -23,6 +23,7 @@
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#include "Porting.h"
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#include "AGESA.h"
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#include "amdlib.h"
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#include <cpu/amd/agesa/s3_resume.h>
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//GNB GPP Port4
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#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable
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@ -33,10 +33,13 @@
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#include "cpuLateInit.h"
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#include "Dispatcher.h"
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#include "cpuCacheInit.h"
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#include "heapManager.h"
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#include "amdlib.h"
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#include "PlatformGnbPcieComplex.h"
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#include "Filecode.h"
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#include <arch/io.h>
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#include <cpu/amd/agesa/s3_resume.h>
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#include <cbmem.h>
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#define FILECODE UNASSIGNED_FILE_FILECODE
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@ -243,6 +246,17 @@ agesawrapper_amdinitearly (
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return (UINT32)status;
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}
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UINT32 GetHeapBase(
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AMD_CONFIG_PARAMS *StdHeader
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)
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{
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UINT32 high_heap;
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high_heap = (UINT32)cbmem_find(CBMEM_ID_RESUME_SCRATCH) + (CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE); /* base + high_stack_size */
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return high_heap;
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}
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UINT32
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agesawrapper_amdinitpost (
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VOID
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@ -272,7 +286,7 @@ agesawrapper_amdinitpost (
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AmdReleaseStruct (&AmdParamStruct);
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/* Initialize heap space */
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BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS;
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BiosManagerPtr = (BIOS_HEAP_MANAGER *)GetHeapBase(&AmdParamStruct.StdHeader);
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HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER));
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for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) {
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@ -496,6 +510,148 @@ agesawrapper_amdinitlate (
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return (UINT32)Status;
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}
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#if CONFIG_HAVE_ACPI_RESUME == 1
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UINT32
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agesawrapper_amdinitresume (
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VOID
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)
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{
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AGESA_STATUS status;
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AMD_INTERFACE_PARAMS AmdParamStruct;
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AMD_RESUME_PARAMS *AmdResumeParamsPtr;
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S3_DATA_TYPE S3DataType;
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LibAmdMemFill (&AmdParamStruct,
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0,
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sizeof (AMD_INTERFACE_PARAMS),
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&(AmdParamStruct.StdHeader));
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AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME;
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AmdParamStruct.AllocationMethod = PreMemHeap;
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AmdParamStruct.StdHeader.AltImageBasePtr = 0;
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AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
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AmdParamStruct.StdHeader.Func = 0;
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AmdParamStruct.StdHeader.ImageBasePtr = 0;
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AmdCreateStruct (&AmdParamStruct);
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AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr;
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AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0;
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AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0;
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S3DataType = S3DataTypeNonVolatile;
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OemAgesaGetS3Info (S3DataType,
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(u32 *) &AmdResumeParamsPtr->S3DataBlock.NvStorageSize,
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(void **) &AmdResumeParamsPtr->S3DataBlock.NvStorage);
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status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr);
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if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
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AmdReleaseStruct (&AmdParamStruct);
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return (UINT32)status;
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}
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UINT32
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agesawrapper_amds3laterestore (
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VOID
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)
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{
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AGESA_STATUS Status;
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AMD_INTERFACE_PARAMS AmdInterfaceParams;
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AMD_S3LATE_PARAMS AmdS3LateParams;
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AMD_S3LATE_PARAMS *AmdS3LateParamsPtr;
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S3_DATA_TYPE S3DataType;
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LibAmdMemFill (&AmdS3LateParams,
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0,
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sizeof (AMD_S3LATE_PARAMS),
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&(AmdS3LateParams.StdHeader));
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AmdInterfaceParams.StdHeader.ImageBasePtr = 0;
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AmdInterfaceParams.AllocationMethod = ByHost;
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AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE;
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AmdInterfaceParams.NewStructPtr = &AmdS3LateParams;
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AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
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AmdS3LateParamsPtr = &AmdS3LateParams;
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AmdInterfaceParams.NewStructSize = sizeof (AMD_S3LATE_PARAMS);
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AmdCreateStruct (&AmdInterfaceParams);
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AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0;
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S3DataType = S3DataTypeVolatile;
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OemAgesaGetS3Info (S3DataType,
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(u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize,
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(void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage);
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Status = AmdS3LateRestore (AmdS3LateParamsPtr);
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if (Status != AGESA_SUCCESS) {
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agesawrapper_amdreadeventlog();
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ASSERT(Status == AGESA_SUCCESS);
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}
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return (UINT32)Status;
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}
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#ifndef __PRE_RAM__
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UINT32
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agesawrapper_amdS3Save (
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VOID
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)
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{
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AGESA_STATUS Status;
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AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr;
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AMD_INTERFACE_PARAMS AmdInterfaceParams;
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S3_DATA_TYPE S3DataType;
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LibAmdMemFill (&AmdInterfaceParams,
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0,
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sizeof (AMD_INTERFACE_PARAMS),
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&(AmdInterfaceParams.StdHeader));
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AmdInterfaceParams.StdHeader.ImageBasePtr = 0;
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AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
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AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
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AmdInterfaceParams.AllocationMethod = PostMemDram;
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AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE;
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AmdInterfaceParams.StdHeader.AltImageBasePtr = 0;
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AmdInterfaceParams.StdHeader.Func = 0;
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AmdCreateStruct(&AmdInterfaceParams);
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AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr;
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AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader;
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Status = AmdS3Save (AmdS3SaveParamsPtr);
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if (Status != AGESA_SUCCESS) {
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agesawrapper_amdreadeventlog();
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ASSERT(Status == AGESA_SUCCESS);
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}
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S3DataType = S3DataTypeNonVolatile;
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Status = OemAgesaSaveS3Info (
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S3DataType,
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AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize,
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AmdS3SaveParamsPtr->S3DataBlock.NvStorage);
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if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) {
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S3DataType = S3DataTypeVolatile;
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Status = OemAgesaSaveS3Info (
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S3DataType,
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AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize,
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AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage
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);
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}
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OemAgesaSaveMtrr();
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AmdReleaseStruct (&AmdInterfaceParams);
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return (UINT32)Status;
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}
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#endif /* #ifndef __PRE_RAM__ */
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#endif /* CONFIG_HAVE_ACPI_RESUME */
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UINT32
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agesawrapper_amdlaterunaptask (
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UINT32 Func,
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@ -84,7 +84,12 @@ UINT32 agesawrapper_amdreadeventlog (void);
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UINT32 agesawrapper_amdinitcpuio (void);
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UINT32 agesawrapper_amdinitmmio (void);
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UINT32 agesawrapper_amdinitresume (void);
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UINT32 agesawrapper_amdS3Save (void);
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UINT32 agesawrapper_amds3laterestore (void);
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UINT32 agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
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void *agesawrapper_getlateinitptr (int pick);
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UINT32 GetHeapBase(AMD_CONFIG_PARAMS *StdHeader);
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#endif
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@ -120,8 +120,8 @@
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#define AGESA_ENTRY_INIT_LATE TRUE
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#define AGESA_ENTRY_INIT_S3SAVE TRUE
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#define AGESA_ENTRY_INIT_RESUME TRUE
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#define AGESA_ENTRY_INIT_LATE_RESTORE FALSE
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#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE
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#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
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#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
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#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
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#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
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@ -169,7 +169,7 @@
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//#define BLDCFG_USE_HT_ASSIST TRUE
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//#define BLDCFG_USE_ATM_MODE TRUE
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//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm
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#define BLDCFG_S3_LATE_RESTORE FALSE
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#define BLDCFG_S3_LATE_RESTORE TRUE
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//#define BLDCFG_USE_32_BYTE_REFRESH FALSE
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//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE
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//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance
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@ -51,6 +51,9 @@ u32 sbdn_sb800;
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static u32 get_bus_conf_done = 0;
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#if CONFIG_HAVE_ACPI_RESUME == 1
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extern u8 acpi_slp_type;
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#endif
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void get_bus_conf(void)
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{
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@ -80,11 +83,20 @@ void get_bus_conf(void)
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* of each of the write functions called prior to the ACPI write functions, so this
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* becomes the best place for this call.
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*/
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#if CONFIG_HAVE_ACPI_RESUME == 1
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if (acpi_slp_type != 3) {
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status = agesawrapper_amdinitlate();
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if(status) {
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if(status)
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printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status);
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status = agesawrapper_amdS3Save();
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if(status)
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printk(BIOS_DEBUG, "agesawrapper_amds3save failed: %x \n", status);
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}
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#else
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status = agesawrapper_amdinitlate();
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if(status)
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printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status);
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#endif
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sbdn_sb800 = 0;
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for (i = 0; i < 3; i++) {
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@ -124,6 +136,7 @@ void get_bus_conf(void)
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for (j = bus_sb800[2]; j < bus_isa; j++)
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bus_type[j] = 1;
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/* I/O APICs: APIC ID Version State Address */
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bus_isa = 10;
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apicid_base = CONFIG_MAX_CPUS;
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@ -23,10 +23,13 @@
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#include <arch/io.h>
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#include <boot/tables.h>
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#include <cpu/x86/msr.h>
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#include <cpu/amd/mtrr.h>
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#include <device/pci_def.h>
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//#include <southbridge/amd/sb800/sb800.h>
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#include <southbridge/amd/sb800/sb800.h>
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#include <arch/acpi.h>
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#include "chip.h"
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#include "BiosCallOuts.h"
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#include <cpu/amd/agesa/s3_resume.h>
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#include <cpu/amd/mtrr.h>
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void set_pcie_reset(void);
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void set_pcie_dereset(void);
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@ -56,6 +59,14 @@ static void persimmon_enable(device_t dev)
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{
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printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
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/*
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* The mainboard is the first place that we get control in ramstage. Check
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* for S3 resume and call the approriate AGESA/CIMx resume functions.
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*/
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#if CONFIG_HAVE_ACPI_RESUME == 1
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acpi_slp_type = acpi_get_sleep_type();
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#endif
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#if (CONFIG_GFXUMA == 1)
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msr_t msr, msr2;
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uint32_t sys_mem;
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@ -110,6 +121,7 @@ int add_mainboard_resources(struct lb_memory *mem)
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#endif
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return 0;
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}
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struct chip_operations mainboard_ops = {
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CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard")
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.enable_dev = persimmon_enable,
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@ -35,9 +35,14 @@
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#include "cpu/x86/lapic/boot_cpu.c"
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#include "pc80/i8254.c"
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#include "pc80/i8259.c"
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#include <cpu/x86/cache.h>
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#include "sb_cimx.h"
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#include "SBPLATFORM.h"
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#include "cbmem.h"
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#include "cpu/amd/mtrr.h"
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#include "cpu/amd/agesa/s3_resume.h"
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void disable_cache_as_ram(void); /* cache_as_ram.inc */
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
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#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1)
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@ -46,6 +51,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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{
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||||
u32 val;
|
||||
|
||||
#if CONFIG_HAVE_ACPI_RESUME == 1
|
||||
void *resume_backup_memory;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* All cores: allow caching of flash chip code and data
|
||||
* (there are no cache-as-ram reliability concerns with family 14h)
|
||||
|
|
@ -98,6 +107,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
|||
else
|
||||
printk(BIOS_DEBUG, "passed.\n");
|
||||
|
||||
#if CONFIG_HAVE_ACPI_RESUME == 1
|
||||
if (!acpi_is_wakeup_early()) { /* Check for S3 resume */
|
||||
#endif
|
||||
post_code(0x40);
|
||||
printk(BIOS_DEBUG, "agesawrapper_amdinitpost ");
|
||||
val = agesawrapper_amdinitpost ();
|
||||
|
|
@ -106,7 +118,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
|||
else
|
||||
printk(BIOS_DEBUG, "passed.\n");
|
||||
|
||||
post_code(0x41);
|
||||
post_code(0x42);
|
||||
printk(BIOS_DEBUG, "agesawrapper_amdinitenv ");
|
||||
val = agesawrapper_amdinitenv ();
|
||||
if (val)
|
||||
|
|
@ -114,12 +126,56 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
|||
else
|
||||
printk(BIOS_DEBUG, "passed.\n");
|
||||
|
||||
#if CONFIG_HAVE_ACPI_RESUME == 1
|
||||
} else { /* S3 detect */
|
||||
printk(BIOS_INFO, "S3 detected\n");
|
||||
|
||||
post_code(0x60);
|
||||
printk(BIOS_DEBUG, "agesawrapper_amdinitresume ");
|
||||
val = agesawrapper_amdinitresume();
|
||||
if (val)
|
||||
printk(BIOS_DEBUG, "error level: %x \n", val);
|
||||
else
|
||||
printk(BIOS_DEBUG, "passed.\n");
|
||||
|
||||
printk(BIOS_DEBUG, "agesawrapper_amds3laterestore ");
|
||||
val = agesawrapper_amds3laterestore ();
|
||||
if (val)
|
||||
printk(BIOS_DEBUG, "error level: %x \n", val);
|
||||
else
|
||||
printk(BIOS_DEBUG, "passed.\n");
|
||||
|
||||
post_code(0x61);
|
||||
printk(BIOS_DEBUG, "Find resume memory location\n");
|
||||
resume_backup_memory = backup_resume();
|
||||
|
||||
post_code(0x62);
|
||||
printk(BIOS_DEBUG, "Move CAR stack.\n");
|
||||
move_stack_high_mem();
|
||||
printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
|
||||
|
||||
post_code(0x63);
|
||||
disable_cache_as_ram();
|
||||
printk(BIOS_DEBUG, "CAR disabled.\n");
|
||||
set_resume_cache();
|
||||
|
||||
/*
|
||||
* Copy the system memory that is in the ramstage area to the
|
||||
* reserved area.
|
||||
*/
|
||||
if (resume_backup_memory)
|
||||
memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
|
||||
|
||||
printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Initialize i8259 pic */
|
||||
post_code(0x41);
|
||||
post_code(0x43);
|
||||
setup_i8259 ();
|
||||
|
||||
/* Initialize i8254 timers */
|
||||
post_code(0x42);
|
||||
post_code(0x44);
|
||||
setup_i8254 ();
|
||||
|
||||
post_code(0x50);
|
||||
|
|
|
|||
Loading…
Reference in New Issue