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nyan: Fix timestamps and CBFS SPI integration 

Nyan is an old board that was committed before several core code
modernizations to timestamp and CBFS code. Not all of those later
patches were correctly integrated with old boards like this, and the
core code has evolved to a point where it doesn't actually boot anymore.

This patch fixes that issue and brings the Nyan boards more in line with
how later ARM platforms look.

BRANCH=None
BUG=None
TEST=My Blaze boots again.

Change-Id: I3277a2f59ad8ed47063f7f6b556685313b1446f8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 6a1679e342a7adc2b2371b6e3f69a898a7a5c717
Original-Change-Id: I2a0a2abbd79b4b5f756125dcbb6cbd9441016d4e
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/328543
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://review.coreboot.org/13832
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit is contained in:
Julius Werner 2016-02-17 16:12:46 -08:00 committed by Patrick Georgi
parent 61980af95d
commit f545208597
6 changed files with 14 additions and 93 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/mainboard/google/nyan/Kconfig
View File

@ -19,6 +19,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y def_bool y
select SOC_NVIDIA_TEGRA124 select SOC_NVIDIA_TEGRA124
select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_CHROMEOS
select COMMON_CBFS_SPI_WRAPPER
select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_SPI select EC_GOOGLE_CHROMEEC_SPI
select TEGRA124_MODEL_CD570M select TEGRA124_MODEL_CD570M
@ -26,6 +27,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select MAINBOARD_DO_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT
select BOARD_ROMSIZE_KB_4096 select BOARD_ROMSIZE_KB_4096
select SPI_FLASH select SPI_FLASH
select SPI_FLASH_GIGADEVICE
select SPI_FLASH_WINBOND
select SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B select SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B
config CHROMEOS config CHROMEOS

3
src/mainboard/google/nyan_big/Kconfig
View File

@ -20,6 +20,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SOC_NVIDIA_TEGRA124 select SOC_NVIDIA_TEGRA124
select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_CHROMEOS
select BOARD_ID_AUTO select BOARD_ID_AUTO
select COMMON_CBFS_SPI_WRAPPER
select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_SPI select EC_GOOGLE_CHROMEEC_SPI
select TEGRA124_MODEL_CD570M select TEGRA124_MODEL_CD570M
@ -27,6 +28,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select MAINBOARD_DO_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT
select BOARD_ROMSIZE_KB_4096 select BOARD_ROMSIZE_KB_4096
select SPI_FLASH select SPI_FLASH
select SPI_FLASH_GIGADEVICE
select SPI_FLASH_WINBOND
select SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B select SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B
config CHROMEOS config CHROMEOS

3
src/mainboard/google/nyan_blaze/Kconfig
View File

@ -19,6 +19,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y def_bool y
select ARCH_ARM select ARCH_ARM
select BOARD_ID_AUTO select BOARD_ID_AUTO
select COMMON_CBFS_SPI_WRAPPER
select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_SPI select EC_GOOGLE_CHROMEEC_SPI
select SOC_NVIDIA_TEGRA124 select SOC_NVIDIA_TEGRA124
@ -28,6 +29,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select MAINBOARD_DO_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT
select BOARD_ROMSIZE_KB_4096 select BOARD_ROMSIZE_KB_4096
select SPI_FLASH select SPI_FLASH
select SPI_FLASH_GIGADEVICE
select SPI_FLASH_WINBOND
select SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B select SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B
config CHROMEOS config CHROMEOS

3
src/soc/nvidia/tegra124/bootblock.c
View File

@ -24,6 +24,7 @@
#include <soc/nvidia/tegra/apbmisc.h> #include <soc/nvidia/tegra/apbmisc.h>
#include <soc/pinmux.h> #include <soc/pinmux.h>
#include <soc/power.h> #include <soc/power.h>
#include <timestamp.h>
#include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/chromeos.h>
static void run_next_stage(void *entry) static void run_next_stage(void *entry)
@ -81,6 +82,8 @@ void main(void)
PINMUX_PWR_INT_N_FUNC_PMICINTR | PINMUX_PWR_INT_N_FUNC_PMICINTR |
PINMUX_INPUT_ENABLE); PINMUX_INPUT_ENABLE);
timestamp_init(0);
run_romstage(); run_romstage();
} }

3
src/soc/nvidia/tegra124/include/soc/memlayout.ld
View File

@ -33,7 +33,8 @@ SECTIONS
STACK(0x4000E000, 8K) STACK(0x4000E000, 8K)
BOOTBLOCK(0x40010000, 24K) BOOTBLOCK(0x40010000, 24K)
VERSTAGE(0x40016000, 72K) VERSTAGE(0x40016000, 72K)
ROMSTAGE(0x40028000, 96K) ROMSTAGE(0x40028000, 95K)
TIMESTAMP(0x4003FC00, 1K)
SRAM_END(0x40040000) SRAM_END(0x40040000)
DRAM_START(0x80000000) DRAM_START(0x80000000)

92
src/soc/nvidia/tegra124/spi.c
View File

@ -798,69 +798,6 @@ int spi_xfer(struct spi_slave *slave, const void *dout,
return ret; return ret;
} }
#define JEDEC_READ 0x03
#define JEDEC_READ_OUTSIZE 0x04
#define JEDEC_FAST_READ_DUAL 0x3b
#define JEDEC_FAST_READ_DUAL_OUTSIZE 0x05
static struct spi_slave *boot_slave;
static ssize_t tegra_spi_readat(const struct region_device *rdev, void *dest,
size_t offset, size_t count)
{
u8 spi_read_cmd[JEDEC_FAST_READ_DUAL_OUTSIZE];
unsigned int read_cmd_bytes;
int ret = count;
struct tegra_spi_channel *channel;
channel = to_tegra_spi(boot_slave->bus);
if (channel->dual_mode) {
/*
* Command 0x3b will interleave data only, command 0xbb will
* interleave the address as well. It's nice to see the address
* plainly when debugging, and we're mostly concerned with
* large transfers so the optimization of using 0xbb isn't
* really worthwhile.
*/
spi_read_cmd[0] = JEDEC_FAST_READ_DUAL;
spi_read_cmd[4] = 0x00; /* dummy byte */
read_cmd_bytes = JEDEC_FAST_READ_DUAL_OUTSIZE;
} else {
spi_read_cmd[0] = JEDEC_READ;
read_cmd_bytes = JEDEC_READ_OUTSIZE;
}
spi_read_cmd[1] = (offset >> 16) & 0xff;
spi_read_cmd[2] = (offset >> 8) & 0xff;
spi_read_cmd[3] = offset & 0xff;
spi_claim_bus(boot_slave);
if (spi_xfer(boot_slave, spi_read_cmd,
read_cmd_bytes, NULL, 0) < 0) {
ret = -1;
printk(BIOS_ERR, "%s: Failed to transfer %u bytes\n",
__func__, sizeof(spi_read_cmd));
goto tegra_spi_cbfs_read_exit;
}
if (channel->dual_mode) {
setbits_le32(&channel->regs->command1, SPI_CMD1_BOTH_EN_BIT);
}
if (spi_xfer(boot_slave, NULL, 0, dest, count)) {
ret = -1;
printk(BIOS_ERR, "%s: Failed to transfer %u bytes\n",
__func__, count);
}
if (channel->dual_mode)
clrbits_le32(&channel->regs->command1, SPI_CMD1_BOTH_EN_BIT);
tegra_spi_cbfs_read_exit:
/* de-assert /CS */
spi_release_bus(boot_slave);
return ret;
}
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs)
{ {
struct tegra_spi_channel *channel = to_tegra_spi(bus); struct tegra_spi_channel *channel = to_tegra_spi(bus);
@ -869,32 +806,3 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs)
return &channel->slave; return &channel->slave;
} }
static const struct region_device_ops tegra_spi_ops = {
.mmap = mmap_helper_rdev_mmap,
.munmap = mmap_helper_rdev_munmap,
.readat = tegra_spi_readat,
};
static struct mmap_helper_region_device mdev =
MMAP_HELPER_REGION_INIT(&tegra_spi_ops, 0, CONFIG_ROM_SIZE);
const struct region_device *boot_device_ro(void)
{
return &mdev.rdev;
}
void boot_device_init(void)
{
struct tegra_spi_channel *boot_chan;
boot_chan = &tegra_spi_channels[CONFIG_BOOT_MEDIA_SPI_BUS - 1];
boot_chan->slave.cs = CONFIG_BOOT_MEDIA_SPI_CHIP_SELECT;
#if CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B == 1
boot_chan->dual_mode = 1;
#endif
boot_slave = &boot_chan->slave;
mmap_helper_device_init(&mdev, _cbfs_cache, _cbfs_cache_size);
}