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AMD boards: constify romstage variables 

That takes them out of .data

Change-Id: Idf88ddaacb2f78ba6a0260e3511b34edc269731d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/7313
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
This commit is contained in:
Patrick Georgi 2014-11-01 10:34:23 +01:00
parent ee6f9813e1
commit f545d71ca2
4 changed files with 11 additions and 11 deletions
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6
src/mainboard/amd/thatcher/PlatformGnbPcie.c
View File

@ -71,7 +71,7 @@
* 38 DP2_TX[P,N]6
*/
PCIe_PORT_DESCRIPTOR PortList [] = {
static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* PCIe port, Lanes 15:8, PCI Device Number 2, PCIE SLOT x8 */
{
0, /* Descriptor flags */
@ -121,7 +121,7 @@ PCIe_PORT_DESCRIPTOR PortList [] = {
},
};
PCIe_DDI_DESCRIPTOR DdiList [] = {
static const PCIe_DDI_DESCRIPTOR DdiList [] = {
// DP0 to HDMI0/DP0
{
0,
@ -142,7 +142,7 @@ PCIe_DDI_DESCRIPTOR DdiList [] = {
},
};
PCIe_COMPLEX_DESCRIPTOR Trinity = {
static const PCIe_COMPLEX_DESCRIPTOR Trinity = {
DESCRIPTOR_TERMINATE_LIST,
0,
&PortList[0],

6
src/mainboard/amd/torpedo/PlatformGnbPcie.c
View File

@ -24,7 +24,7 @@
#define FILECODE PROC_GNB_PCIE_FAMILY_0X12_F12PCIECOMPLEXCONFIG_FILECODE
PCIe_PORT_DESCRIPTOR PortList [] = {
static const PCIe_PORT_DESCRIPTOR PortList [] = {
// Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...)
{
0, //Descriptor flags
@ -69,7 +69,7 @@ PCIe_PORT_DESCRIPTOR PortList [] = {
// }
};
PCIe_DDI_DESCRIPTOR DdiList [] = {
static const PCIe_DDI_DESCRIPTOR DdiList [] = {
// Initialize Ddi descriptor (DDI interface Lanes 24:27, DdA, ...)
{
0, //Descriptor flags
@ -84,7 +84,7 @@ PCIe_DDI_DESCRIPTOR DdiList [] = {
}
};
PCIe_COMPLEX_DESCRIPTOR Llano = {
static const PCIe_COMPLEX_DESCRIPTOR Llano = {
DESCRIPTOR_TERMINATE_LIST,
0,
&PortList[0],

4
src/mainboard/amd/torpedo/gpio.h
View File

@ -1995,7 +1995,7 @@ typedef struct _GPIO_SETTINGS
u8 NonGpioGevent;
} GPIO_SETTINGS;
GPIO_SETTINGS gpio_table[]=
const GPIO_SETTINGS gpio_table[]=
{
{GPIO_00_SELECT, GPIO_00_TYPE, GPO_00_LEVEL+GPIO_00_STICKY+GPIO_00_PULLUP+GPIO_00_PULLDOWN, GPIO_00_SELECT},
{GPIO_01_SELECT, GPIO_01_TYPE, GPO_01_LEVEL+GPIO_01_STICKY+GPIO_01_PULLUP+GPIO_01_PULLDOWN, GPIO_01_SELECT},
@ -2269,7 +2269,7 @@ typedef struct _GEVENT_SETTINGS
u8 SmiControl; // 0: Disable, 1: SMI 2: NMI 3: IRQ13
} GEVENT_SETTINGS;
GEVENT_SETTINGS gevent_table[] =
const GEVENT_SETTINGS gevent_table[] =
{
{GEVENT_00_EVENTENABLE, GEVENT_00_SCITRIG, GEVENT_00_SCILEVEL, GEVENT_00_SMISCIEN, GEVENT_00_SCIS0EN, GEVENT_00_SCIMAP, GEVENT_00_SMITRIG, GEVENT_00_SMICONTROL},
{GEVENT_01_EVENTENABLE, GEVENT_01_SCITRIG, GEVENT_01_SCILEVEL, GEVENT_01_SMISCIEN, GEVENT_01_SCIS0EN, GEVENT_01_SCIMAP, GEVENT_01_SMITRIG, GEVENT_01_SMICONTROL},

6
src/mainboard/asus/f2a85-m/PlatformGnbPcie.c
View File

@ -68,7 +68,7 @@
* 38 DP2_TX[P,N]6
*/
PCIe_PORT_DESCRIPTOR PortList [] = {
static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* PCIe port, Lanes 8:23, PCI Device Number 2, blue x16 slot */
{
0, /* Descriptor flags */
@ -95,7 +95,7 @@ PCIe_PORT_DESCRIPTOR PortList [] = {
* Tested and works: VGA/DVI
* Untested: HDMI
*/
PCIe_DDI_DESCRIPTOR DdiList [] = {
static const PCIe_DDI_DESCRIPTOR DdiList [] = {
// DP0 to HDMI0/DP
{
0,
@ -116,7 +116,7 @@ PCIe_DDI_DESCRIPTOR DdiList [] = {
},
};
PCIe_COMPLEX_DESCRIPTOR Trinity = {
static const PCIe_COMPLEX_DESCRIPTOR Trinity = {
DESCRIPTOR_TERMINATE_LIST,
0,
&PortList[0],