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nb/intel/sandybridge: add and use ME stolen memory and lock bit defines 

Change-Id: If4663498b10a5eedcc1aa51088b984ecc49ef23e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Felix Held 2019-12-30 18:18:02 +01:00
parent 7c09c6a960
commit f54ae3875f
3 changed files with 5 additions and 3 deletions
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2
src/northbridge/intel/sandybridge/finalize.c
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@ -24,7 +24,7 @@ void intel_sandybridge_finalize_smm(void)
pci_or_config16(PCI_DEV_SNB, GGC, 1 << 0); pci_or_config16(PCI_DEV_SNB, GGC, 1 << 0);
pci_or_config16(PCI_DEV_SNB, PAVPC, 1 << 2); pci_or_config16(PCI_DEV_SNB, PAVPC, 1 << 2);
pci_or_config32(PCI_DEV_SNB, DPR, 1 << 0); pci_or_config32(PCI_DEV_SNB, DPR, 1 << 0);
pci_or_config32(PCI_DEV_SNB, MESEG_MASK, 1 << 10); pci_or_config32(PCI_DEV_SNB, MESEG_MASK, MELCK);
pci_or_config32(PCI_DEV_SNB, REMAPBASE, 1 << 0); pci_or_config32(PCI_DEV_SNB, REMAPBASE, 1 << 0);
pci_or_config32(PCI_DEV_SNB, REMAPLIMIT, 1 << 0); pci_or_config32(PCI_DEV_SNB, REMAPLIMIT, 1 << 0);
pci_or_config32(PCI_DEV_SNB, TOM, 1 << 0); pci_or_config32(PCI_DEV_SNB, TOM, 1 << 0);

4
src/northbridge/intel/sandybridge/raminit_common.c
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@ -608,8 +608,8 @@ void dram_memorymap(ramctr_timing * ctrl, int me_uma_size)
reg = pci_read_config32(PCI_DEV(0, 0, 0), MESEG_MASK); reg = pci_read_config32(PCI_DEV(0, 0, 0), MESEG_MASK);
val = (0x80000 - me_uma_size) & 0xfff; val = (0x80000 - me_uma_size) & 0xfff;
reg = (reg & ~0xfff00000) | (val << 20); reg = (reg & ~0xfff00000) | (val << 20);
reg = reg | (1 << 10); // set lockbit on ME mem reg = reg | ME_STLEN_EN; // set ME memory enable
reg = reg | (1 << 11); // set ME memory enable reg = reg | MELCK; // set lockbit on ME mem
printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_MASK, reg); printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_MASK, reg);
pci_write_config32(PCI_DEV(0, 0, 0), MESEG_MASK, reg); pci_write_config32(PCI_DEV(0, 0, 0), MESEG_MASK, reg);
} }

2
src/northbridge/intel/sandybridge/sandybridge.h
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@ -83,6 +83,8 @@ enum platform_type {
#define MESEG_BASE 0x70 #define MESEG_BASE 0x70
#define MESEG_MASK 0x78 #define MESEG_MASK 0x78
#define MELCK (1 << 10) /* ME Range Lock */
#define ME_STLEN_EN (1 << 11) /* ME Stolen Memory Enable */
#define PAM0 0x80 #define PAM0 0x80
#define PAM1 0x81 #define PAM1 0x81