nb/intel/sandybridge: Fix description of auto-precharge bit

This bit is primarily used to issue RDA commands. There doesn't seem to
be any limitation regarding the number of address bits.

Change-Id: I2804f67319c9bc736f9086af408853056aabedd6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50473
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

src/northbridge/intel/sandybridge/raminit_common.c

@@ -1711,7 +1711,7 @@ static void train_write_flyby(ramctr_timing *ctrl)
 					.rank    = slotrank,
 				},
 			},
-			/* DRAM command RD */
+			/* DRAM command RDA */
 			[2] = {
 				.sp_cmd_ctrl = {
 					.command    = IOSAV_RD,

src/northbridge/intel/sandybridge/registers/mchbar.h

@@ -112,7 +112,7 @@
  *          end architecture RTL;
  *
  *   [16]       Chip Select mode control.
- *   [17]       Auto Precharge. Only valid when using 10 row bits!
+ *   [17]       Auto Precharge. Used to send RDA commands.
  *
  * IOSAV_n_SUBSEQ_CTRL_ch(channel, index)
  *   The parameters of the subseq: number of repetitions of the command,