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mb/google/brya: Skip locking for GPP_F14 GPIO 

This is regarding issues observed on multiple Brya and Nissa
variant such as Skolas and Nivviks. Issue is that once coreboot
sets GPE_EN bit for the GPIO pin and locks it, kernel is not able
to change the control bit. Hence kernel is not able to control the
IRQ on the pin when required.

This issue was root caused to the patch which was setting GPE_EN
bits for the GPIOs before locking.
Ref: commit 38b8bf02d8
("intelblocks: Add function to program GPE_EN before GPIO locking")

This patch skips the locking for GPP_F14 to allow kernel to
configure it later during reboot or shutdown as required.

BUG=b:254064671
BRANCH=None
TEST=Shutdown works on Skolas and Brya board with the patch.

Signed-off-by: Maulik Vaghela <maulikvaghela@google.com>
Change-Id: I7e4a6ac4668028bcd5fa400b9aa8eccf36a79620
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72648
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Maulik Vaghela 2023-01-31 14:44:56 +00:00 committed by Felix Held
parent 32d2d5c776
commit f564c8b34a
1 changed files with 1 additions and 1 deletions
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2
src/mainboard/google/brya/variants/baseboard/brya/gpio.c
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@ -240,7 +240,7 @@ static const struct pad_config gpio_table[] = {
/* F13 : GSXDOUT ==> GSPI_PCH_DI_FPMCU_DO */ /* F13 : GSXDOUT ==> GSPI_PCH_DI_FPMCU_DO */
PAD_CFG_NF_LOCK(GPP_F13, NONE, NF4, LOCK_CONFIG), PAD_CFG_NF_LOCK(GPP_F13, NONE, NF4, LOCK_CONFIG),
/* F14 : GSXDIN ==> TCHPAD_INT_ODL */ /* F14 : GSXDIN ==> TCHPAD_INT_ODL */
PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F14, NONE, LEVEL, INVERT, LOCK_CONFIG), PAD_CFG_GPI_IRQ_WAKE(GPP_F14, NONE, PWROK, LEVEL, INVERT),
/* F15 : GSXSRESET# ==> FPMCU_INT_L */ /* F15 : GSXSRESET# ==> FPMCU_INT_L */
PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F15, NONE, LEVEL, INVERT, LOCK_CONFIG), PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F15, NONE, LEVEL, INVERT, LOCK_CONFIG),
/* F16 : GSXCLK ==> GSPI_PCH_CS_FPMCU_R_L */ /* F16 : GSXCLK ==> GSPI_PCH_CS_FPMCU_R_L */