soc/amd/picasso: Rename SD_EMMC_EMMC_DDR_52 to SD_EMMC_EMMC_DDR_104

The number at the end actually means the max MiB/s. So 52 MHz clock @ 8x
data width, sampled on each clock edge = 104 MiB/s.

According to JEDEC Standard No. 84-B51A (JESD84-B51A), maximum bandwidth
& clock frequency for various MMC bus speed modes are (at x8 bus width):
MMC_Legacy: 26 MB/s at 26 MHz Single Data Rate (SDR)
MMC_HS: 52 MB/s at 52 MHz SDR
MMC_DDR52: 104 MB/s at 52 MHz Dual Data Rate (DDR)
MMC_HS200: 200 MB/s at 200 MHz SDR
MMC_HS400: 400 MB/s at 200 MHz DDR

BUG=b:159823235
BRANCH=zork
TEST=build zork

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7818d8cb5ed5974c60a900477a0aa2ecc904db0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48309
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/amd/picasso/chip.h

@@ -175,7 +175,7 @@ struct soc_amd_picasso_config {
 			SD_EMMC_SD_UHS_I_SDR_104,
 			SD_EMMC_EMMC_SDR_26,
 			SD_EMMC_EMMC_SDR_52,
-			SD_EMMC_EMMC_DDR_52,
+			SD_EMMC_EMMC_DDR_104,
 			SD_EMMC_EMMC_HS200,
 			SD_EMMC_EMMC_HS400,
 			SD_EMMC_EMMC_HS300,

src/soc/amd/picasso/fsp_params.c

@@ -38,8 +38,8 @@ static void fsps_update_emmc_config(FSP_S_CONFIG *scfg,
 	case SD_EMMC_EMMC_SDR_52:
 		val = EMMC_SDR_52;
 		break;
-	case SD_EMMC_EMMC_DDR_52:
+	case SD_EMMC_EMMC_DDR_104:
-		val = EMMC_DDR_52;
+		val = EMMC_DDR_104;
 		break;
 	case SD_EMMC_EMMC_HS200:
 		val = EMMC_HS200;

src/soc/amd/picasso/include/soc/platform_descriptors.h

@@ -17,7 +17,7 @@
 #define SD_UHS_I_SDR_104	5
 #define EMMC_SDR_26		6
 #define EMMC_SDR_52		7
-#define EMMC_DDR_52		8
+#define EMMC_DDR_104		8
 #define EMMC_HS200		9
 #define EMMC_HS400		10
 #define EMMC_HS300		11