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Hudson: Cleanup - change SB800 references to hudson 

Go through southbridge/amd/agesa/hudson, thatcher and parmer
mainboard directories and change all references to sb800 to
reference hudson instead.

This is just cleanup and should make no functional difference.

Change-Id: Icd6a9a08c4bbf5e1aed394362d24c05811ed1fba
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2177
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
This commit is contained in:
Martin Roth 2013-01-18 12:55:40 -07:00
parent 2892023fd4
commit f5726ea544
17 changed files with 95 additions and 101 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/amd/parmer/acpi_tables.c
View File

@ -62,7 +62,7 @@ unsigned long acpi_fill_madt(unsigned long current)
/* create all subtables for processors */ /* create all subtables for processors */
current = acpi_create_madt_lapics(current); current = acpi_create_madt_lapics(current);
/* Write SB800 IOAPIC, only one */ /* Write Hudson IOAPIC, only one */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,
IO_APIC_ADDR, 0); IO_APIC_ADDR, 0);

2
src/mainboard/amd/parmer/agesawrapper.c
View File

@ -100,7 +100,7 @@ agesawrapper_amdinitcpuio (
PciData = 1; PciData = 1;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* The platform BIOS needs to ensure the memory ranges of SB800 legacy /* The platform BIOS needs to ensure the memory ranges of Hudson legacy
* devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
* set to non-posted regions. * set to non-posted regions.
*/ */

2
src/mainboard/amd/parmer/dsdt.asl
View File

@ -188,7 +188,7 @@ DefinitionBlock (
PM2D, 0x00000008, PM2D, 0x00000008,
} }
/* Power Management I/O registers, TODO:PMIO is quite different in SB800. */ /* Power Management I/O registers. */
OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
Field(PIOR, ByteAcc, NoLock, Preserve) { Field(PIOR, ByteAcc, NoLock, Preserve) {
PIOI, 0x00000008, PIOI, 0x00000008,

29
src/mainboard/amd/parmer/get_bus_conf.c
View File

@ -30,8 +30,8 @@
* and acpi_tables busnum is default. * and acpi_tables busnum is default.
*/ */
u8 bus_isa; u8 bus_isa;
u8 bus_sb800[3]; u8 bus_hudson[3];
u32 apicid_sb800; u32 apicid_hudson;
/* /*
* Here you only need to set value in pci1234 for HT-IO that could be installed or not * Here you only need to set value in pci1234 for HT-IO that could be installed or not
@ -43,7 +43,7 @@ u32 pci1234x[] = {
}; };
u32 bus_type[256]; u32 bus_type[256];
u32 sbdn_sb800; u32 sbdn_hudson;
static u32 get_bus_conf_done = 0; static u32 get_bus_conf_done = 0;
@ -95,10 +95,10 @@ void get_bus_conf(void)
printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status);
#endif #endif
sbdn_sb800 = 0; sbdn_hudson = 0;
for (i = 0; i < 3; i++) { for (i = 0; i < 3; i++) {
bus_sb800[i] = 0; bus_hudson[i] = 0;
} }
for (i = 0; i < 256; i++) { for (i = 0; i < 256; i++) {
@ -107,34 +107,33 @@ void get_bus_conf(void)
bus_type[0] = 1; /* pci */ bus_type[0] = 1; /* pci */
// bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff; bus_hudson[0] = (pci1234x[0] >> 16) & 0xff;
bus_sb800[0] = (pci1234x[0] >> 16) & 0xff;
/* sb800 */ /* Hudson */
dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4)); dev = dev_find_slot(bus_hudson[0], PCI_DEVFN(sbdn_hudson + 0x14, 4));
if (dev) { if (dev) {
bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_hudson[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++; bus_isa++;
for (j = bus_sb800[1]; j < bus_isa; j++) for (j = bus_hudson[1]; j < bus_isa; j++)
bus_type[j] = 1; bus_type[j] = 1;
} }
for (i = 0; i < 4; i++) { for (i = 0; i < 4; i++) {
dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, i)); dev = dev_find_slot(bus_hudson[0], PCI_DEVFN(sbdn_hudson + 0x14, i));
if (dev) { if (dev) {
bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_hudson[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++; bus_isa++;
} }
} }
for (j = bus_sb800[2]; j < bus_isa; j++) for (j = bus_hudson[2]; j < bus_isa; j++)
bus_type[j] = 1; bus_type[j] = 1;
/* I/O APICs: APIC ID Version State Address */ /* I/O APICs: APIC ID Version State Address */
bus_isa = 10; bus_isa = 10;
apicid_base = CONFIG_MAX_CPUS; apicid_base = CONFIG_MAX_CPUS;
apicid_sb800 = apicid_base; apicid_hudson = apicid_base;
} }

10
src/mainboard/amd/parmer/irq_tables.c
View File

@ -44,8 +44,8 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
} }
extern u8 bus_isa; extern u8 bus_isa;
extern u8 bus_sb800[2]; extern u8 bus_hudson[2];
extern unsigned long sbdn_sb800; extern unsigned long sbdn_hudson;
unsigned long write_pirq_routing_table(unsigned long addr) unsigned long write_pirq_routing_table(unsigned long addr)
{ {
@ -72,8 +72,8 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq->signature = PIRQ_SIGNATURE; pirq->signature = PIRQ_SIGNATURE;
pirq->version = PIRQ_VERSION; pirq->version = PIRQ_VERSION;
pirq->rtr_bus = bus_sb800[0]; pirq->rtr_bus = bus_hudson[0];
pirq->rtr_devfn = ((sbdn_sb800 + 0x14) << 3) | 4; pirq->rtr_devfn = ((sbdn_hudson + 0x14) << 3) | 4;
pirq->exclusive_irqs = 0; pirq->exclusive_irqs = 0;
@ -88,7 +88,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
slot_num = 0; slot_num = 0;
/* pci bridge */ /* pci bridge */
write_pirq_info(pirq_info, bus_sb800[0], ((sbdn_sb800 + 0x14) << 3) | 4, write_pirq_info(pirq_info, bus_hudson[0], ((sbdn_hudson + 0x14) << 3) | 4,
0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
0); 0);
pirq_info++; pirq_info++;

44
src/mainboard/amd/parmer/mptable.c
View File

@ -30,11 +30,11 @@
//-#define IO_APIC_ID CONFIG_MAX_PHYSICAL_CPUS + 1 //-#define IO_APIC_ID CONFIG_MAX_PHYSICAL_CPUS + 1
#define IO_APIC_ID CONFIG_MAX_CPUS #define IO_APIC_ID CONFIG_MAX_CPUS
extern u8 bus_sb800[3]; extern u8 bus_hudson[3];
extern u32 bus_type[256]; extern u32 bus_type[256];
extern u32 sbdn_sb800; extern u32 sbdn_hudson;
extern u32 apicid_sb800; extern u32 apicid_hudson;
u8 picr_data[0x54] = { u8 picr_data[0x54] = {
0x1F,0x1f,0x1f,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, 0x1F,0x1f,0x1f,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
@ -103,8 +103,8 @@ static void *smp_write_config_table(void *v)
/* Set IO APIC ID onto IO_APIC_ID */ /* Set IO APIC ID onto IO_APIC_ID */
write32 (dword, 0x00); write32 (dword, 0x00);
write32 (dword + 0x10, IO_APIC_ID << 24); write32 (dword + 0x10, IO_APIC_ID << 24);
apicid_sb800 = IO_APIC_ID; apicid_hudson = IO_APIC_ID;
smp_write_ioapic(mc, apicid_sb800, 0x21, dword); smp_write_ioapic(mc, apicid_hudson, 0x21, dword);
/* PIC IRQ routine */ /* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) { for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
@ -121,13 +121,13 @@ static void *smp_write_config_table(void *v)
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \ #define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0); mptable_add_isa_interrupts(mc, bus_isa, apicid_hudson, 0);
/* PCI interrupts are level triggered, and are /* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple. * associated with a specific bus/device/function tuple.
*/ */
#define PCI_INT(bus, dev, int_sign, pin) \ #define PCI_INT(bus, dev, int_sign, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb800, (pin)) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_hudson, (pin))
/* Internal VGA */ /* Internal VGA */
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
@ -156,26 +156,26 @@ static void *smp_write_config_table(void *v)
/* PCI slots */ /* PCI slots */
/* PCI_SLOT 0. */ /* PCI_SLOT 0. */
PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14); PCI_INT(bus_hudson[1], 0x5, 0x0, 0x14);
PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15); PCI_INT(bus_hudson[1], 0x5, 0x1, 0x15);
PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16); PCI_INT(bus_hudson[1], 0x5, 0x2, 0x16);
PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17); PCI_INT(bus_hudson[1], 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */ /* PCI_SLOT 1. */
PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15); PCI_INT(bus_hudson[1], 0x6, 0x0, 0x15);
PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16); PCI_INT(bus_hudson[1], 0x6, 0x1, 0x16);
PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17); PCI_INT(bus_hudson[1], 0x6, 0x2, 0x17);
PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14); PCI_INT(bus_hudson[1], 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */ /* PCI_SLOT 2. */
PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16); PCI_INT(bus_hudson[1], 0x7, 0x0, 0x16);
PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17); PCI_INT(bus_hudson[1], 0x7, 0x1, 0x17);
PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14); PCI_INT(bus_hudson[1], 0x7, 0x2, 0x14);
PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15); PCI_INT(bus_hudson[1], 0x7, 0x3, 0x15);
PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12); PCI_INT(bus_hudson[2], 0x0, 0x0, 0x12);
PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13); PCI_INT(bus_hudson[2], 0x0, 0x1, 0x13);
PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14); PCI_INT(bus_hudson[2], 0x0, 0x2, 0x14);
/* PCIe Lan*/ /* PCIe Lan*/
PCI_INT(0x0, 0x06, 0x0, 0x13); PCI_INT(0x0, 0x06, 0x0, 0x13);

4
src/mainboard/amd/parmer/romstage.c
View File

@ -68,14 +68,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
post_code(0x37); post_code(0x37);
printk(BIOS_DEBUG, "agesawrapper_amdinitreset ");
val = agesawrapper_amdinitreset(); val = agesawrapper_amdinitreset();
if(val) { if(val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val); printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val);
} }
post_code(0x38);
printk(BIOS_DEBUG, "Got past sb800_early_setup\n");
post_code(0x39); post_code(0x39);
val = agesawrapper_amdinitearly (); val = agesawrapper_amdinitearly ();

2
src/mainboard/amd/thatcher/acpi_tables.c
View File

@ -62,7 +62,7 @@ unsigned long acpi_fill_madt(unsigned long current)
/* create all subtables for processors */ /* create all subtables for processors */
current = acpi_create_madt_lapics(current); current = acpi_create_madt_lapics(current);
/* Write SB800 IOAPIC, only one */ /* Write Hudson IOAPIC, only one */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,
IO_APIC_ADDR, 0); IO_APIC_ADDR, 0);

2
src/mainboard/amd/thatcher/agesawrapper.c
View File

@ -100,7 +100,7 @@ agesawrapper_amdinitcpuio (
PciData = 1; PciData = 1;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* The platform BIOS needs to ensure the memory ranges of SB800 legacy /* The platform BIOS needs to ensure the memory ranges of Hudson legacy
* devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
* set to non-posted regions. * set to non-posted regions.
*/ */

2
src/mainboard/amd/thatcher/dsdt.asl
View File

@ -188,7 +188,7 @@ DefinitionBlock (
PM2D, 0x00000008, PM2D, 0x00000008,
} }
/* Power Management I/O registers, TODO:PMIO is quite different in SB800. */ /* Power Management I/O registers. */
OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
Field(PIOR, ByteAcc, NoLock, Preserve) { Field(PIOR, ByteAcc, NoLock, Preserve) {
PIOI, 0x00000008, PIOI, 0x00000008,

29
src/mainboard/amd/thatcher/get_bus_conf.c
View File

@ -30,8 +30,8 @@
* and acpi_tables busnum is default. * and acpi_tables busnum is default.
*/ */
u8 bus_isa; u8 bus_isa;
u8 bus_sb800[3]; u8 bus_hudson[3];
u32 apicid_sb800; u32 apicid_hudson;
/* /*
* Here you only need to set value in pci1234 for HT-IO that could be installed or not * Here you only need to set value in pci1234 for HT-IO that could be installed or not
@ -43,7 +43,7 @@ u32 pci1234x[] = {
}; };
u32 bus_type[256]; u32 bus_type[256];
u32 sbdn_sb800; u32 sbdn_hudson;
static u32 get_bus_conf_done = 0; static u32 get_bus_conf_done = 0;
@ -95,10 +95,10 @@ void get_bus_conf(void)
printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status);
#endif #endif
sbdn_sb800 = 0; sbdn_hudson = 0;
for (i = 0; i < 3; i++) { for (i = 0; i < 3; i++) {
bus_sb800[i] = 0; bus_hudson[i] = 0;
} }
for (i = 0; i < 256; i++) { for (i = 0; i < 256; i++) {
@ -107,34 +107,33 @@ void get_bus_conf(void)
bus_type[0] = 1; /* pci */ bus_type[0] = 1; /* pci */
// bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff; bus_hudson[0] = (pci1234x[0] >> 16) & 0xff;
bus_sb800[0] = (pci1234x[0] >> 16) & 0xff;
/* sb800 */ /* Hudson */
dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4)); dev = dev_find_slot(bus_hudson[0], PCI_DEVFN(sbdn_hudson + 0x14, 4));
if (dev) { if (dev) {
bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_hudson[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++; bus_isa++;
for (j = bus_sb800[1]; j < bus_isa; j++) for (j = bus_hudson[1]; j < bus_isa; j++)
bus_type[j] = 1; bus_type[j] = 1;
} }
for (i = 0; i < 4; i++) { for (i = 0; i < 4; i++) {
dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, i)); dev = dev_find_slot(bus_hudson[0], PCI_DEVFN(sbdn_hudson + 0x14, i));
if (dev) { if (dev) {
bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_hudson[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++; bus_isa++;
} }
} }
for (j = bus_sb800[2]; j < bus_isa; j++) for (j = bus_hudson[2]; j < bus_isa; j++)
bus_type[j] = 1; bus_type[j] = 1;
/* I/O APICs: APIC ID Version State Address */ /* I/O APICs: APIC ID Version State Address */
bus_isa = 10; bus_isa = 10;
apicid_base = CONFIG_MAX_CPUS; apicid_base = CONFIG_MAX_CPUS;
apicid_sb800 = apicid_base; apicid_hudson = apicid_base;
} }

10
src/mainboard/amd/thatcher/irq_tables.c
View File

@ -44,8 +44,8 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
} }
extern u8 bus_isa; extern u8 bus_isa;
extern u8 bus_sb800[2]; extern u8 bus_hudson[2];
extern unsigned long sbdn_sb800; extern unsigned long sbdn_hudson;
unsigned long write_pirq_routing_table(unsigned long addr) unsigned long write_pirq_routing_table(unsigned long addr)
{ {
@ -72,8 +72,8 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq->signature = PIRQ_SIGNATURE; pirq->signature = PIRQ_SIGNATURE;
pirq->version = PIRQ_VERSION; pirq->version = PIRQ_VERSION;
pirq->rtr_bus = bus_sb800[0]; pirq->rtr_bus = bus_hudson[0];
pirq->rtr_devfn = ((sbdn_sb800 + 0x14) << 3) | 4; pirq->rtr_devfn = ((sbdn_hudson + 0x14) << 3) | 4;
pirq->exclusive_irqs = 0; pirq->exclusive_irqs = 0;
@ -88,7 +88,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
slot_num = 0; slot_num = 0;
/* pci bridge */ /* pci bridge */
write_pirq_info(pirq_info, bus_sb800[0], ((sbdn_sb800 + 0x14) << 3) | 4, write_pirq_info(pirq_info, bus_hudson[0], ((sbdn_hudson + 0x14) << 3) | 4,
0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
0); 0);
pirq_info++; pirq_info++;

44
src/mainboard/amd/thatcher/mptable.c
View File

@ -30,11 +30,11 @@
//-#define IO_APIC_ID CONFIG_MAX_PHYSICAL_CPUS + 1 //-#define IO_APIC_ID CONFIG_MAX_PHYSICAL_CPUS + 1
#define IO_APIC_ID CONFIG_MAX_CPUS #define IO_APIC_ID CONFIG_MAX_CPUS
extern u8 bus_sb800[3]; extern u8 bus_hudson[3];
extern u32 bus_type[256]; extern u32 bus_type[256];
extern u32 sbdn_sb800; extern u32 sbdn_hudson;
extern u32 apicid_sb800; extern u32 apicid_hudson;
u8 picr_data[] = { u8 picr_data[] = {
0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
@ -103,8 +103,8 @@ static void *smp_write_config_table(void *v)
/* Set IO APIC ID onto IO_APIC_ID */ /* Set IO APIC ID onto IO_APIC_ID */
write32 (dword, 0x00); write32 (dword, 0x00);
write32 (dword + 0x10, IO_APIC_ID << 24); write32 (dword + 0x10, IO_APIC_ID << 24);
apicid_sb800 = IO_APIC_ID; apicid_hudson = IO_APIC_ID;
smp_write_ioapic(mc, apicid_sb800, 0x21, dword); smp_write_ioapic(mc, apicid_hudson, 0x21, dword);
/* PIC IRQ routine */ /* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) { for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
@ -121,13 +121,13 @@ static void *smp_write_config_table(void *v)
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \ #define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0); mptable_add_isa_interrupts(mc, bus_isa, apicid_hudson, 0);
/* PCI interrupts are level triggered, and are /* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple. * associated with a specific bus/device/function tuple.
*/ */
#define PCI_INT(bus, dev, int_sign, pin) \ #define PCI_INT(bus, dev, int_sign, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb800, (pin)) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_hudson, (pin))
/* Internal VGA */ /* Internal VGA */
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
@ -156,26 +156,26 @@ static void *smp_write_config_table(void *v)
/* PCI slots */ /* PCI slots */
/* PCI_SLOT 0. */ /* PCI_SLOT 0. */
PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14); PCI_INT(bus_hudson[1], 0x5, 0x0, 0x14);
PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15); PCI_INT(bus_hudson[1], 0x5, 0x1, 0x15);
PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16); PCI_INT(bus_hudson[1], 0x5, 0x2, 0x16);
PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17); PCI_INT(bus_hudson[1], 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */ /* PCI_SLOT 1. */
PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15); PCI_INT(bus_hudson[1], 0x6, 0x0, 0x15);
PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16); PCI_INT(bus_hudson[1], 0x6, 0x1, 0x16);
PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17); PCI_INT(bus_hudson[1], 0x6, 0x2, 0x17);
PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14); PCI_INT(bus_hudson[1], 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */ /* PCI_SLOT 2. */
PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16); PCI_INT(bus_hudson[1], 0x7, 0x0, 0x16);
PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17); PCI_INT(bus_hudson[1], 0x7, 0x1, 0x17);
PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14); PCI_INT(bus_hudson[1], 0x7, 0x2, 0x14);
PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15); PCI_INT(bus_hudson[1], 0x7, 0x3, 0x15);
PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12); PCI_INT(bus_hudson[2], 0x0, 0x0, 0x12);
PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13); PCI_INT(bus_hudson[2], 0x0, 0x1, 0x13);
PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14); PCI_INT(bus_hudson[2], 0x0, 0x2, 0x14);
/* PCIe Lan*/ /* PCIe Lan*/
PCI_INT(0x0, 0x06, 0x0, 0x13); PCI_INT(0x0, 0x06, 0x0, 0x13);

4
src/mainboard/amd/thatcher/romstage.c
View File

@ -85,14 +85,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
post_code(0x37); post_code(0x37);
printk(BIOS_DEBUG, "agesawrapper_amdinitreset ");
val = agesawrapper_amdinitreset(); val = agesawrapper_amdinitreset();
if(val) { if(val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val); printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val);
} }
post_code(0x38);
printk(BIOS_DEBUG, "Got past sb800_early_setup\n");
post_code(0x39); post_code(0x39);
val = agesawrapper_amdinitearly (); val = agesawrapper_amdinitearly ();

2
src/southbridge/amd/agesa/hudson/hudson.c
View File

@ -99,7 +99,7 @@ u8 pm2_ioread(u8 reg)
void hudson_enable(device_t dev) void hudson_enable(device_t dev)
{ {
printk(BIOS_DEBUG, "sb800_enable()\n"); printk(BIOS_DEBUG, "hudson_enable()\n");
} }
struct cbmem_entry *get_cbmem_toc(void) struct cbmem_entry *get_cbmem_toc(void)

4
src/southbridge/amd/agesa/hudson/smbus.c
View File

@ -17,8 +17,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#ifndef _SB800_SMBUS_C_ #ifndef _HUDSON_SMBUS_C_
#define _SB800_SMBUS_C_ #define _HUDSON_SMBUS_C_
#include "smbus.h" #include "smbus.h"

4
src/southbridge/amd/agesa/hudson/smbus.h
View File

@ -17,8 +17,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#ifndef SB800_SMBUS_H #ifndef HUDSON_SMBUS_H
#define SB800_SMBUS_H #define HUDSON_SMBUS_H
//#include <stdint.h> //#include <stdint.h>