ARM: Use LPAE for Virtual Address Translation
This change introduces LPAE for virtual address translation. To enable it, set ARM_LPAE. Boot slows down about 4ms on Tegra124 with LPAE enabled. TEST=Booted nyan with and without LPAE. Built nyan_big and daisy. BUG=None BRANCH=none Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@google.com> Original-Change-Id: I74aa729b6fe6d243f57123dc792302359c661cad Original-Reviewed-on: https://chromium-review.googlesource.com/187862 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit 6d8c8b2bbdc70555076081eb3bfaabde7b4a398f) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I8980375c14758af35f7d5ec5244be963e5462d8a Reviewed-on: http://review.coreboot.org/7749 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
This commit is contained in:
Daisuke Nojiri
Marc Jones
parent
032c843817
commit
f574a327ee
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@ -30,4 +30,8 @@ config CPU_HAS_BOOTBLOCK_INIT
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config MAINBOARD_HAS_BOOTBLOCK_INIT
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bool
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default n
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default n
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config ARM_LPAE
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bool "Enable LPAE"
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default n
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@ -27,6 +27,7 @@
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* SUCH DAMAGE.
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*/
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#include <assert.h>
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#include <config.h>
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#include <stdlib.h>
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#include <stdint.h>
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@ -37,32 +38,29 @@
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#include <arch/cache.h>
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#include <arch/io.h>
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static void *const ttb_buff = (void *)CONFIG_TTB_BUFFER;
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#if CONFIG_ARM_LPAE
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/* See B3.6.2 of ARMv7 Architecture Reference Manual */
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/* TODO: Utilize the contiguous hint flag */
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#define ATTR_BASE (\
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0ULL << 54 | /* PN. 0:Not restricted */ \
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0ULL << 53 | /* PXN. 0:Not restricted */ \
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1 << 10 | /* AF. 1:Accessed. This is to prevent access \
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* fault when accessed for the first time */ \
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0 << 6 | /* AP[2:1]. 0b00:full access from PL1 */ \
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0 << 5 | /* NS. 0:Output address is in Secure space */ \
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0 << 1 | /* block/table. 0:block entry */ \
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1 << 0 /* validity. 1:valid */ \
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)
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#define ATTR_NC (ATTR_BASE | (MAIR_INDX_NC << 2))
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#define ATTR_WT (ATTR_BASE | (MAIR_INDX_WT << 2))
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#define ATTR_WB (ATTR_BASE | (MAIR_INDX_WB << 2))
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void mmu_disable_range(unsigned long start_mb, unsigned long size_mb)
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{
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unsigned int i;
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uint32_t *ttb_entry = ttb_buff;
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printk(BIOS_DEBUG, "Disabling: 0x%08lx:0x%08lx\n",
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start_mb*MiB, start_mb*MiB + size_mb*MiB - 1);
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for (i = start_mb; i < start_mb + size_mb; i++)
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writel(0, &ttb_entry[i]);
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for (i = start_mb; i < start_mb + size_mb; i++) {
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dccmvac((uintptr_t)&ttb_entry[i]);
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tlbimvaa(i*MiB);
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}
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}
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void mmu_config_range(unsigned long start_mb, unsigned long size_mb,
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enum dcache_policy policy)
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{
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unsigned int i;
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uint32_t attr;
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uint32_t *ttb_entry = ttb_buff;
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const char *str = NULL;
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#define BLOCK_SHIFT 21
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typedef uint64_t pgd_t;
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typedef uint64_t pmd_t;
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static const unsigned int denom = 2;
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#else /* CONFIG_ARM_LPAE */
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/*
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* Section entry bits:
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* 31:20 - section base address
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@ -79,19 +77,83 @@ void mmu_config_range(unsigned long start_mb, unsigned long size_mb,
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* 2 - B, 1 for bufferable
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* 1: 0 - 0b10 to indicate section entry
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*/
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#define ATTR_BASE ((3 << 10) | 0x2)
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#define ATTR_NC (ATTR_BASE | (1 << 4))
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#define ATTR_WT (ATTR_BASE | (1 << 3))
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#define ATTR_WB (ATTR_BASE | (1 << 3) | (1 << 2))
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#define BLOCK_SHIFT 20
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typedef uint32_t pgd_t;
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typedef uint32_t pmd_t;
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static const unsigned int denom = 1;
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#endif /* CONFIG_ARM_LPAE */
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static pmd_t *const ttb_buff = (pmd_t *)CONFIG_TTB_BUFFER;
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/*
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* mask/shift/size for pages and blocks
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*/
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#define PAGE_SHIFT 12
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#define PAGE_SIZE (1UL << PAGE_SHIFT)
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#define PAGE_MASK ~((1UL << PAGE_SHIFT) - 1)
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#define BLOCK_SIZE (1UL << BLOCK_SHIFT)
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/*
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* MAIR Index
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*/
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#define MAIR_INDX_NC 0
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#define MAIR_INDX_WT 1
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#define MAIR_INDX_WB 2
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static void mmu_flush_page_table_entry_range(
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unsigned long start_mb, unsigned long size_mb)
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{
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int i;
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/* Flush the page table entries from the dcache. */
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for (i = start_mb/denom; i*denom < start_mb + size_mb; i++)
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dccmvac((uintptr_t)&ttb_buff[i]);
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dsb();
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/* Invalidate the TLB entries. */
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for (i = start_mb/denom; i*denom < start_mb + size_mb; i++)
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tlbimvaa(i*denom*MiB);
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dsb();
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isb();
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}
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void mmu_disable_range(unsigned long start_mb, unsigned long size_mb)
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{
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int i;
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printk(BIOS_DEBUG, "Disabling: [0x%08lx:0x%08lx)\n",
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start_mb*MiB, start_mb*MiB + size_mb*MiB);
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for (i = start_mb/denom; i*denom < start_mb + size_mb; i++)
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ttb_buff[i] = 0;
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mmu_flush_page_table_entry_range(start_mb, size_mb);
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}
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void mmu_config_range(unsigned long start_mb, unsigned long size_mb,
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enum dcache_policy policy)
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{
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const char *str = NULL;
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pmd_t attr;
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int i;
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switch(policy) {
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case DCACHE_OFF:
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/* XN set to avoid prefetches to uncached/unbuffered regions */
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attr = (0x3 << 10) | (1 << 4) | 0x2;
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attr = ATTR_NC;
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str = "off";
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break;
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case DCACHE_WRITEBACK:
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attr = (0x3 << 10) | (1 << 3) | (1 << 2) | 0x2;
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attr = ATTR_WB;
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str = "writeback";
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break;
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case DCACHE_WRITETHROUGH:
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attr = (0x3 << 10) | (1 << 3) | 0x2;
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attr = ATTR_WT;
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str = "writethrough";
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break;
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default:
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@ -99,52 +161,86 @@ void mmu_config_range(unsigned long start_mb, unsigned long size_mb,
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return;
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}
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printk(BIOS_DEBUG, "Setting dcache policy: 0x%08lx:0x%08lx [%s]\n",
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start_mb << 20, ((start_mb + size_mb) << 20) - 1, str);
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printk(BIOS_DEBUG, "Setting dcache policy: [0x%08lx:0x%08lx) [%s]\n",
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start_mb << 20, ((start_mb + size_mb) << 20), str);
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/* Write out page table entries. */
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for (i = start_mb; i < start_mb + size_mb; i++)
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writel((i << 20) | attr, &ttb_entry[i]);
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for (i = start_mb/denom; i*denom < start_mb + size_mb; i++)
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ttb_buff[i] = ((pmd_t)i << BLOCK_SHIFT) | attr;
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/* Flush the page table entries from the dcache. */
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for (i = start_mb; i < start_mb + size_mb; i++)
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dccmvac((uintptr_t)&ttb_entry[i]);
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dsb();
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/* Invalidate the TLB entries. */
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for (i = start_mb; i < start_mb + size_mb; i++)
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tlbimvaa(i*MiB);
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dsb();
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isb();
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mmu_flush_page_table_entry_range(start_mb, size_mb);
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}
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/*
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* For coreboot's purposes, we will create a simple identity map.
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*
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* If LPAE is disabled, we will create a L1 page
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* table in RAM with 1MB section translation entries over the 4GB address space.
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* (ref: section 10.2 and example 15-4 in Cortex-A series programmer's guide)
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*
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* If LPAE is enabled, we do two level translation with one L1 table with 4
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* entries, each covering a 1GB space, and four L2 tables with 512 entries, each
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* covering a 2MB space.
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*/
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void mmu_init(void)
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{
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/*
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* For coreboot's purposes, we will create a simple L1 page table
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* in RAM with 1MB section translation entries over the 4GB address
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* space.
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* (ref: section 10.2 and example 15-4 in Cortex-A series
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* programmer's guide)
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*/
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printk(BIOS_DEBUG, "Translation table is @ %p\n", ttb_buff);
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if (CONFIG_ARM_LPAE) {
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pgd_t *const pgd_buff = (pgd_t*)(CONFIG_TTB_BUFFER + 16*KiB);
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pmd_t *pmd = ttb_buff;
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int i;
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printk(BIOS_DEBUG, "LPAE Translation tables are @ %p\n",
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ttb_buff);
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ASSERT((read_mmfr0() & 0xf) >= 5);
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/*
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* Set MAIR
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* See B4.1.104 of ARMv7 Architecture Reference Manual
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*/
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write_mair0(
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0x00 << (MAIR_INDX_NC*8) | /* Strongly-ordered,
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* Non-Cacheable */
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0xaa << (MAIR_INDX_WT*8) | /* Write-Thru,
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* Read-Allocate */
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0xff << (MAIR_INDX_WB*8) /* Write-Back,
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* Read/Write-Allocate */
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);
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/*
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* Set up L1 table
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* Once set here, L1 table won't be modified by coreboot.
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* See B3.6.1 of ARMv7 Architecture Reference Manual
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*/
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for (i = 0; i < 4; i++) {
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pgd_buff[i] = ((uint32_t)pmd & PAGE_MASK) |
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3; /* 0b11: valid table entry */
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pmd += BLOCK_SIZE / PAGE_SIZE;
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}
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/*
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* Set TTBR0
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*/
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write_ttbr0((uintptr_t)pgd_buff);
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} else {
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printk(BIOS_DEBUG, "Translation table is @ %p\n", ttb_buff);
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/*
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* Translation table base 0 address is in bits 31:14-N, where N
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* is given by bits 2:0 in TTBCR (which we set to 0). All lower
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* bits in this register should be zero for coreboot.
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*/
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write_ttbr0((uintptr_t)ttb_buff);
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}
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/*
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* Disable TTBR1 by setting TTBCR.N to 0b000, which means the TTBR0
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* table size is 16KB and has indices VA[31:20].
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*
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* ref: Arch Ref. Manual for ARMv7-A, B3.5.4,
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* Set TTBCR
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* See B4.1.153 of ARMv7 Architecture Reference Manual
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* See B3.5.4 and B3.6.4 for how TTBR0 or TTBR1 is selected.
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*/
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write_ttbcr(read_ttbcr() & ~0x3);
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/*
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* Translation table base 0 address is in bits 31:14-N, where N is given
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* by bits 2:0 in TTBCR (which we set to 0). All lower bits in this
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* register should be zero for coreboot.
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*/
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write_ttbr0((uintptr_t)ttb_buff);
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write_ttbcr(
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CONFIG_ARM_LPAE << 31 | /* EAE. 1:Enable LPAE */
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0 << 16 | 0 << 0 /* Use TTBR0 for all addresses */
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);
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/* disable domain-level checking of permissions */
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write_dacr(~0);
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@ -111,10 +111,34 @@ static inline void write_dacr(uint32_t val)
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asm volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (val));
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}
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/* read memory model feature register 0 (MMFR0) */
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static inline uint32_t read_mmfr0(void)
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{
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uint32_t mmfr;
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asm volatile ("mrc p15, 0, %0, c0, c1, 4" : "=r" (mmfr));
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return mmfr;
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}
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/* read MAIR0 (memory address indirection register 0) */
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static inline uint32_t read_mair0(void)
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{
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uint32_t mair;
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asm volatile ("mrc p15, 0, %0, c10, c2, 0" : "=r" (mair));
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return mair;
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}
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/* write MAIR0 (memory address indirection register 0) */
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static inline void write_mair0(uint32_t val)
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{
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asm volatile ("mcr p15, 0, %0, c10, c2, 0" : : "r" (val));
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}
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/* write translation table base register 0 (TTBR0) */
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static inline void write_ttbr0(uint32_t val)
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{
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#if CONFIG_ARM_LPAE
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asm volatile ("mcrr p15, 0, %[val], %[zero], c2" : :
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[val] "r" (val), [zero] "r" (0));
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#else
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asm volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (val) : "memory");
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#endif
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}
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/* read translation table base control register (TTBCR) */
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@ -1,4 +1,6 @@
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config SOC_NVIDIA_TEGRA124
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bool
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default n
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select ARCH_BOOTBLOCK_ARMV4
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select ARCH_ROMSTAGE_ARMV7
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select ARCH_RAMSTAGE_ARMV7
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@ -6,8 +8,8 @@ config SOC_NVIDIA_TEGRA124
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select BOOTBLOCK_CONSOLE
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select DYNAMIC_CBMEM
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select ARM_BOOTBLOCK_CUSTOM
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bool
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default n
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select ARM_LPAE
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if SOC_NVIDIA_TEGRA124
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@ -31,8 +33,7 @@ config BOOTBLOCK_CPU_INIT
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# handoff that area may be reclaimed for other uses, e.g. CBFS cache.)
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#
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# 0x4000_0000 TTB (16K+32B). 32B is for L1 table of LPAE.
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# 0x4000_4020 CBMEM console area (8K-32B)
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# 0x4000_6000 CBFS mapping cache (88K)
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# 0x4000_4020 CBFS mapping cache (96K-32B)
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# 0x4001_C000 Stack (16KB... don't reduce without comparing LZMA scratchpad!).
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# 0x4002_0000 Bootblock (max 48KB).
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# 0x4002_C000 ROM stage (max 80KB).
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@ -86,15 +87,11 @@ config TTB_BUFFER
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config CBFS_CACHE_ADDRESS
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hex "memory address to put CBFS cache data"
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default 0x40006000
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default 0x40004020
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config CBFS_CACHE_SIZE
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hex "size of CBFS cache data"
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default 0x00016000
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config CBMEM_CONSOLE_PRERAM_BASE
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hex "memory address of the CBMEM console buffer"
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default 0x40004020
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default 0x00017fe0
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config TEGRA124_MODEL_TD570D
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bool "TD570D"
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