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soc/intel/common/../cse: Append `_MS` with CSE_DELAY_BOOT_TO_RO macro 

CSE_DELAY_BOOT_TO_RO -> CSE_DELAY_BOOT_TO_RO_MS

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I4471e4553a081eaf5c8118e9600497a2b2437ac0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Subrata Banik 2021-09-30 13:37:10 +05:30
parent c543a81736
commit f576581954
1 changed files with 3 additions and 4 deletions
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7
src/soc/intel/common/block/cse/cse.c
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@ -29,6 +29,8 @@
#define HECI_READ_TIMEOUT_MS (5 * 1000) #define HECI_READ_TIMEOUT_MS (5 * 1000)
/* Wait up to 1 ms for CSE CIP */ /* Wait up to 1 ms for CSE CIP */
#define HECI_CIP_TIMEOUT_US 1000 #define HECI_CIP_TIMEOUT_US 1000
/* Wait up to 5 seconds for CSE to boot from RO(BP1) */
#define CSE_DELAY_BOOT_TO_RO_MS (5 * 1000)
#define SLOT_SIZE sizeof(uint32_t) #define SLOT_SIZE sizeof(uint32_t)
@ -62,9 +64,6 @@
#define MEI_HDR_CSE_ADDR_START 0 #define MEI_HDR_CSE_ADDR_START 0
#define MEI_HDR_CSE_ADDR (((1 << 8) - 1) << MEI_HDR_CSE_ADDR_START) #define MEI_HDR_CSE_ADDR (((1 << 8) - 1) << MEI_HDR_CSE_ADDR_START)
/* Wait up to 5 seconds for CSE to boot from RO(BP1) */
#define CSE_DELAY_BOOT_TO_RO (5 * 1000)
static struct cse_device { static struct cse_device {
uintptr_t sec_bar; uintptr_t sec_bar;
} cse; } cse;
@ -306,7 +305,7 @@ uint8_t cse_wait_sec_override_mode(void)
uint8_t cse_wait_com_soft_temp_disable(void) uint8_t cse_wait_com_soft_temp_disable(void)
{ {
struct stopwatch sw; struct stopwatch sw;
stopwatch_init_msecs_expire(&sw, CSE_DELAY_BOOT_TO_RO); stopwatch_init_msecs_expire(&sw, CSE_DELAY_BOOT_TO_RO_MS);
while (!cse_is_hfs1_com_soft_temp_disable()) { while (!cse_is_hfs1_com_soft_temp_disable()) {
udelay(HECI_DELAY_US); udelay(HECI_DELAY_US);
if (stopwatch_expired(&sw)) { if (stopwatch_expired(&sw)) {