soc/intel: Drop casts around `soc_read_pmc_base()`

The `soc_read_pmc_base()` function returns an `uintptr_t`, which is then
casted to a pointer type for use with `read32()` and/or `write32()`. But
since commit b324df6a54 (arch/x86: Provide
readXp/writeXp helpers in arch/mmio.h), the `read32p()` and `write32p()`
functions live in `arch/mmio.h`. These functions use the `uintptr_t type
for the address parameter instead of a pointer type, and using them with
the `soc_read_pmc_base()` function allows dropping the casts to pointer.

Change-Id: Iaf16e6f23d139e6f79360d9a29576406b7b15b07
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>

src/soc/intel/alderlake/acpi.c

@@ -167,7 +167,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
 
 uint32_t soc_read_sci_irq_select(void)
 {
-	return read32((void *)soc_read_pmc_base() + IRQ_REG);
+	return read32p(soc_read_pmc_base() + IRQ_REG);
 }
 
 static unsigned long soc_fill_dmar(unsigned long current)

src/soc/intel/apollolake/acpi.c

@@ -54,14 +54,12 @@ static acpi_cstate_t cstate_map[] = {
 
 uint32_t soc_read_sci_irq_select(void)
 {
-	uintptr_t pmc_bar = soc_read_pmc_base();
-	return read32((void *)pmc_bar + IRQ_REG);
+	return read32p(soc_read_pmc_base() + IRQ_REG);
 }
 
 void soc_write_sci_irq_select(uint32_t scis)
 {
-	uintptr_t pmc_bar = soc_read_pmc_base();
-	write32((void *)pmc_bar + IRQ_REG, scis);
+	write32p(soc_read_pmc_base() + IRQ_REG, scis);
 }
 
 acpi_cstate_t *soc_get_cstate_map(size_t *entries)

src/soc/intel/apollolake/pmc.c

@@ -71,10 +71,10 @@ static void set_slp_s3_assertion_width(int width_usecs)
 	uintptr_t gen_pmcon3 = soc_read_pmc_base() + GEN_PMCON3;
 	int setting = choose_slp_s3_assertion_width(width_usecs);
 
-	reg = read32((void *)gen_pmcon3);
+	reg = read32p(gen_pmcon3);
 	reg &= ~SLP_S3_ASSERT_MASK;
 	reg |= setting << SLP_S3_ASSERT_WIDTH_SHIFT;
-	write32((void *)gen_pmcon3, reg);
+	write32p(gen_pmcon3, reg);
 }
 
 void pmc_soc_init(struct device *dev)

src/soc/intel/apollolake/pmutil.c

@@ -227,13 +227,13 @@ uint16_t get_pmbase(void)
 
 void pmc_soc_set_afterg3_en(const bool on)
 {
-	void *const gen_pmcon1 = (void *)(soc_read_pmc_base() + GEN_PMCON1);
+	const uintptr_t gen_pmcon1 = soc_read_pmc_base() + GEN_PMCON1;
 	uint32_t reg32;
 
-	reg32 = read32(gen_pmcon1);
+	reg32 = read32p(gen_pmcon1);
 	if (on)
 		reg32 &= ~SLEEP_AFTER_POWER_FAIL;
 	else
 		reg32 |= SLEEP_AFTER_POWER_FAIL;
-	write32(gen_pmcon1, reg32);
+	write32p(gen_pmcon1, reg32);
 }

src/soc/intel/cannonlake/acpi.c

@@ -166,8 +166,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
 }
 uint32_t soc_read_sci_irq_select(void)
 {
-	uintptr_t pmc_bar = soc_read_pmc_base();
-	return read32((void *)pmc_bar + IRQ_REG);
+	return read32p(soc_read_pmc_base() + IRQ_REG);
 }
 
 void soc_fill_gnvs(struct global_nvs *gnvs)

src/soc/intel/common/block/pmc/pmclib.c

@@ -368,8 +368,8 @@ void pmc_clear_prsts(void)
 	/* Read PMC base address from soc */
 	pmc_bar = soc_read_pmc_base();
 
-	prsts = read32((void *)(pmc_bar + PRSTS));
-	write32((void *)(pmc_bar + PRSTS), prsts);
+	prsts = read32p(pmc_bar + PRSTS);
+	write32p(pmc_bar + PRSTS, prsts);
 
 	soc_clear_pm_registers(pmc_bar);
 }
@@ -559,7 +559,7 @@ void pmc_gpe_init(void)
 	 */
 	if (dw0 == dw1 || dw1 == dw2) {
 		printk(BIOS_INFO, "PMC: Using default GPE route.\n");
-		gpio_cfg = read32((void *)pmc_bar + GPIO_GPE_CFG);
+		gpio_cfg = read32p(pmc_bar + GPIO_GPE_CFG);
 
 		dw0 = (gpio_cfg >> GPE0_DW_SHIFT(0)) & GPE0_DWX_MASK;
 		dw1 = (gpio_cfg >> GPE0_DW_SHIFT(1)) & GPE0_DWX_MASK;
@@ -570,10 +570,10 @@ void pmc_gpe_init(void)
 		gpio_cfg |= (uint32_t) dw2 << GPE0_DW_SHIFT(2);
 	}
 
-	gpio_cfg_reg = read32((void *)pmc_bar + GPIO_GPE_CFG) & ~gpio_cfg_mask;
+	gpio_cfg_reg = read32p(pmc_bar + GPIO_GPE_CFG) & ~gpio_cfg_mask;
 	gpio_cfg_reg |= gpio_cfg & gpio_cfg_mask;
 
-	write32((void *)pmc_bar + GPIO_GPE_CFG, gpio_cfg_reg);
+	write32p(pmc_bar + GPIO_GPE_CFG, gpio_cfg_reg);
 
 	/* Set the routes in the GPIO communities as well. */
 	gpio_route_gpe(dw0, dw1, dw2);

src/soc/intel/elkhartlake/acpi.c

@@ -171,8 +171,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
 
 uint32_t soc_read_sci_irq_select(void)
 {
-	uintptr_t pmc_bar = soc_read_pmc_base();
-	return read32((void *)pmc_bar + IRQ_REG);
+	return read32p(soc_read_pmc_base() + IRQ_REG);
 }
 
 static unsigned long soc_fill_dmar(unsigned long current)

src/soc/intel/icelake/acpi.c

@@ -162,8 +162,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
 }
 uint32_t soc_read_sci_irq_select(void)
 {
-	uintptr_t pmc_bar = soc_read_pmc_base();
-	return read32((void *)pmc_bar + IRQ_REG);
+	return read32p(soc_read_pmc_base() + IRQ_REG);
 }
 
 void soc_fill_gnvs(struct global_nvs *gnvs)

src/soc/intel/jasperlake/acpi.c

@@ -166,8 +166,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
 
 uint32_t soc_read_sci_irq_select(void)
 {
-	uintptr_t pmc_bar = soc_read_pmc_base();
-	return read32((void *)pmc_bar + IRQ_REG);
+	return read32p(soc_read_pmc_base() + IRQ_REG);
 }
 
 static unsigned long soc_fill_dmar(unsigned long current)

src/soc/intel/tigerlake/acpi.c

@@ -166,8 +166,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
 
 uint32_t soc_read_sci_irq_select(void)
 {
-	uintptr_t pmc_bar = soc_read_pmc_base();
-	return read32((void *)pmc_bar + IRQ_REG);
+	return read32p(soc_read_pmc_base() + IRQ_REG);
 }
 
 static unsigned long soc_fill_dmar(unsigned long current)