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mb/siemens/mc_ehl3/gpio.c: Disable PSE GBE0 GPIO 

Since the PSE GBE0 MAC has been disabled on this board in
commit 343644006f ("mb/siemens/mc_ehl3/devicetree.cb:
Remove TSN GbE 0"), therefore disable the corresponding
GPIOs as well.

BUG=none
TEST=Test link detection and IP assignment on the remaining
ports (PSE GBE1 and PCH GBE0) of mc_ehl3.

Change-Id: Ifa055f58894688471d68b9b93fcb994fdcb2a568
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72449
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Jan Samek 2023-01-26 10:14:55 +01:00 committed by Paul Fagerburg
parent 6ac0a46bbf
commit f58abca47a
1 changed files with 18 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
src/mainboard/siemens/mc_ehl/variants/mc_ehl3/gpio.c
View File

@ -20,10 +20,10 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_B23, NONE), /* Not connected */
/* Community 0 - GpioGroup GPP_T */
PAD_CFG_NF(GPP_T4, NONE, DEEP, NF1), /* PSE_GBE0_INT */
PAD_CFG_GPO(GPP_T5, 1, DEEP), /* PSE_GBE0_RST_N */
PAD_CFG_NF(GPP_T6, NONE, DEEP, NF1), /* PSE_GBE0_AUXTS */
PAD_CFG_NF(GPP_T7, NONE, DEEP, NF1), /* PSE_GBE0_PPS */
PAD_NC(GPP_T4, NONE), /* Not connected */
PAD_NC(GPP_T5, NONE), /* Not connected */
PAD_NC(GPP_T6, NONE), /* Not connected */
PAD_NC(GPP_T7, NONE), /* Not connected */
PAD_CFG_NF(GPP_T12, NONE, DEEP, NF2), /* SIO_UART0_RXD */
PAD_CFG_NF(GPP_T13, NONE, DEEP, NF2), /* SIO_UART0_TXD */
@ -80,17 +80,17 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_S1, NONE), /* Not connected */
/* Community 3 - GpioGroup GPP_A */
PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXD3 */
PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXD2 */
PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXD1 */
PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXD0 */
PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXCLK */
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXCTL */
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXCLK */
PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXD3 */
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXD2 */
PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXD1 */
PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXD0 */
PAD_NC(GPP_A0, NONE), /* Not connected */
PAD_NC(GPP_A1, NONE), /* Not connected */
PAD_NC(GPP_A2, NONE), /* Not connected */
PAD_NC(GPP_A3, NONE), /* Not connected */
PAD_NC(GPP_A4, NONE), /* Not connected */
PAD_NC(GPP_A5, NONE), /* Not connected */
PAD_NC(GPP_A6, NONE), /* Not connected */
PAD_NC(GPP_A7, NONE), /* Not connected */
PAD_NC(GPP_A8, NONE), /* Not connected */
PAD_NC(GPP_A9, NONE), /* Not connected */
PAD_NC(GPP_A10, NONE), /* Not connected */
PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_TXD3 */
PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_TXD2 */
PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_TXD1 */
@ -103,11 +103,11 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_RXD2 */
PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_RXD1 */
PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1), /* PSE_GBE1_RGMII_RXD0 */
PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXCTL */
PAD_NC(GPP_A23, NONE), /* Not connected */
/* Community 4 - GpioGroup GPP_C */
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* PSE_GBE0_MDC */
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* PSE_GBE0_MDIO */
PAD_NC(GPP_C3, NONE), /* Not connected */
PAD_NC(GPP_C4, NONE), /* Not connected */
PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* PSE_GBE0_AUXTS */
PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* PSE_GBE0_PPS */
PAD_CFG_NF(GPP_C12, NONE, DEEP, NF4), /* SIO_UART1_RXD */