diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h
index 492a401eea..204d073365 100644
--- a/src/soc/intel/elkhartlake/chip.h
+++ b/src/soc/intel/elkhartlake/chip.h
@@ -240,6 +240,12 @@ struct soc_intel_elkhartlake_config {
 	/* PCIe RP L1 substate */
 	enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS];
 
+	/* PCIe root port maximum payload size, default is set to 128 bytes. */
+	enum {
+		RpMaxPayload_128,
+		RpMaxPayload_256,
+	} PcieRpMaxPayload[CONFIG_MAX_ROOT_PORTS];
+
 	/* PCIe root port speed. 0: Auto (Default); 1: Gen1; 2: Gen2; 3: Gen3 */
 	uint8_t PcieRpPcieSpeed[CONFIG_MAX_ROOT_PORTS];
 
diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c
index a3213b151c..5e1bba78ea 100644
--- a/src/soc/intel/elkhartlake/fsp_params.c
+++ b/src/soc/intel/elkhartlake/fsp_params.c
@@ -388,6 +388,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 		params->PcieRpVc1TcMap[i] = 0x60;
 		if (config->realtime_tuning_enable)
 			params->PcieRpEnableCpm[i] = 0;
+		params->PcieRpMaxPayload[i] = config->PcieRpMaxPayload[i];
 	}
 
 	/* SATA config */