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mb: Move timestamp_add_now to northbridge x4x 

Change-Id: Iacbee658a4049e1c13a120dbc21425ffb6a1cabb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Elyes HAOUAS 2019-01-08 22:15:53 +01:00 committed by Kyösti Mälkki
parent ab4eb2afc3
commit f5a57a883b
9 changed files with 7 additions and 57 deletions
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7
src/mainboard/asrock/g41c-gs/romstage.c
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@ -25,10 +25,8 @@
#include <superio/winbond/w83627dhg/w83627dhg.h> #include <superio/winbond/w83627dhg/w83627dhg.h>
#include <superio/winbond/common/winbond.h> #include <superio/winbond/common/winbond.h>
#include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/common/nuvoton.h>
#include <lib.h>
#include <northbridge/intel/x4x/iomap.h> #include <northbridge/intel/x4x/iomap.h>
#include <device/pnp_def.h> #include <device/pnp_def.h>
#include <timestamp.h>
#define SERIAL_DEV_R2 PNP_DEV(0x2e, NCT6776_SP1) #define SERIAL_DEV_R2 PNP_DEV(0x2e, NCT6776_SP1)
#define SERIAL_DEV_R1 PNP_DEV(0x2e, W83627DHG_SP1) #define SERIAL_DEV_R1 PNP_DEV(0x2e, W83627DHG_SP1)
@ -106,12 +104,7 @@ void mainboard_romstage_entry(unsigned long bist)
if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET)
boot_path = BOOT_PATH_WARM_RESET; boot_path = BOOT_PATH_WARM_RESET;
printk(BIOS_DEBUG, "Initializing memory\n");
timestamp_add_now(TS_BEFORE_INITRAM);
sdram_initialize(boot_path, spd_addrmap); sdram_initialize(boot_path, spd_addrmap);
timestamp_add_now(TS_AFTER_INITRAM);
quick_ram_check();
printk(BIOS_DEBUG, "Memory initialized\n");
x4x_late_init(s3_resume); x4x_late_init(s3_resume);

7
src/mainboard/asus/p5qc/romstage.c
View File

@ -23,9 +23,7 @@
#include <cpu/intel/romstage.h> #include <cpu/intel/romstage.h>
#include <superio/winbond/w83667hg-a/w83667hg-a.h> #include <superio/winbond/w83667hg-a/w83667hg-a.h>
#include <superio/winbond/common/winbond.h> #include <superio/winbond/common/winbond.h>
#include <lib.h>
#include <northbridge/intel/x4x/iomap.h> #include <northbridge/intel/x4x/iomap.h>
#include <timestamp.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83667HG_A_SP1) #define SERIAL_DEV PNP_DEV(0x2e, W83667HG_A_SP1)
#define LPC_DEV PCI_DEV(0, 0x1f, 0) #define LPC_DEV PCI_DEV(0, 0x1f, 0)
@ -91,12 +89,7 @@ void mainboard_romstage_entry(unsigned long bist)
if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET)
boot_path = BOOT_PATH_WARM_RESET; boot_path = BOOT_PATH_WARM_RESET;
printk(BIOS_DEBUG, "Initializing memory\n");
timestamp_add_now(TS_BEFORE_INITRAM);
sdram_initialize(boot_path, spd_addrmap); sdram_initialize(boot_path, spd_addrmap);
timestamp_add_now(TS_AFTER_INITRAM);
quick_ram_check();
printk(BIOS_DEBUG, "Memory initialized\n");
x4x_late_init(s3_resume); x4x_late_init(s3_resume);

7
src/mainboard/asus/p5qpl-am/romstage.c
View File

@ -23,10 +23,8 @@
#include <cpu/intel/romstage.h> #include <cpu/intel/romstage.h>
#include <superio/winbond/w83627dhg/w83627dhg.h> #include <superio/winbond/w83627dhg/w83627dhg.h>
#include <superio/winbond/common/winbond.h> #include <superio/winbond/common/winbond.h>
#include <lib.h>
#include <northbridge/intel/x4x/iomap.h> #include <northbridge/intel/x4x/iomap.h>
#include <device/pnp_def.h> #include <device/pnp_def.h>
#include <timestamp.h>
#include <halt.h> #include <halt.h>
#include <cpu/intel/speedstep.h> #include <cpu/intel/speedstep.h>
#include <cpu/x86/msr.h> #include <cpu/x86/msr.h>
@ -171,12 +169,7 @@ void mainboard_romstage_entry(unsigned long bist)
halt(); halt();
} }
printk(BIOS_DEBUG, "Initializing memory\n");
timestamp_add_now(TS_BEFORE_INITRAM);
sdram_initialize(boot_path, spd_addrmap); sdram_initialize(boot_path, spd_addrmap);
timestamp_add_now(TS_AFTER_INITRAM);
quick_ram_check();
printk(BIOS_DEBUG, "Memory initialized\n");
x4x_late_init(s3_resume); x4x_late_init(s3_resume);

7
src/mainboard/foxconn/g41s-k/romstage.c
View File

@ -24,8 +24,6 @@
#include <southbridge/intel/i82801gx/i82801gx.h> #include <southbridge/intel/i82801gx/i82801gx.h>
#include <superio/ite/common/ite.h> #include <superio/ite/common/ite.h>
#include <superio/ite/it8720f/it8720f.h> #include <superio/ite/it8720f/it8720f.h>
#include <lib.h>
#include <timestamp.h>
#define LPC_DEV PCI_DEV(0, 0x1f, 0) #define LPC_DEV PCI_DEV(0, 0x1f, 0)
#define SERIAL_DEV PNP_DEV(0x2e, IT8720F_SP1) #define SERIAL_DEV PNP_DEV(0x2e, IT8720F_SP1)
@ -105,12 +103,7 @@ void mainboard_romstage_entry(unsigned long bist)
if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET)
boot_path = BOOT_PATH_WARM_RESET; boot_path = BOOT_PATH_WARM_RESET;
printk(BIOS_DEBUG, "Initializing memory\n");
timestamp_add_now(TS_BEFORE_INITRAM);
sdram_initialize(boot_path, spd_addrmap); sdram_initialize(boot_path, spd_addrmap);
timestamp_add_now(TS_AFTER_INITRAM);
quick_ram_check();
printk(BIOS_DEBUG, "Memory initialized\n");
x4x_late_init(s3_resume); x4x_late_init(s3_resume);

8
src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
View File

@ -15,7 +15,6 @@
*/ */
#include <stdint.h> #include <stdint.h>
#include <stdlib.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <arch/io.h> #include <arch/io.h>
#include <device/pnp_def.h> #include <device/pnp_def.h>
@ -27,9 +26,7 @@
#include <cpu/intel/romstage.h> #include <cpu/intel/romstage.h>
#include <superio/ite/it8718f/it8718f.h> #include <superio/ite/it8718f/it8718f.h>
#include <superio/ite/common/ite.h> #include <superio/ite/common/ite.h>
#include <lib.h>
#include <northbridge/intel/x4x/iomap.h> #include <northbridge/intel/x4x/iomap.h>
#include <timestamp.h>
#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO)
@ -153,12 +150,7 @@ void mainboard_romstage_entry(unsigned long bist)
if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET)
boot_path = BOOT_PATH_WARM_RESET; boot_path = BOOT_PATH_WARM_RESET;
printk(BIOS_DEBUG, "Initializing memory\n");
timestamp_add_now(TS_BEFORE_INITRAM);
sdram_initialize(boot_path, spd_addrmap); sdram_initialize(boot_path, spd_addrmap);
timestamp_add_now(TS_AFTER_INITRAM);
quick_ram_check();
printk(BIOS_DEBUG, "Memory initialized\n");
x4x_late_init(s3_resume); x4x_late_init(s3_resume);

7
src/mainboard/intel/dg41wv/romstage.c
View File

@ -23,10 +23,8 @@
#include <cpu/intel/romstage.h> #include <cpu/intel/romstage.h>
#include <superio/winbond/w83627dhg/w83627dhg.h> #include <superio/winbond/w83627dhg/w83627dhg.h>
#include <superio/winbond/common/winbond.h> #include <superio/winbond/common/winbond.h>
#include <lib.h>
#include <northbridge/intel/x4x/iomap.h> #include <northbridge/intel/x4x/iomap.h>
#include <device/pnp_def.h> #include <device/pnp_def.h>
#include <timestamp.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
#define LPC_DEV PCI_DEV(0, 0x1f, 0) #define LPC_DEV PCI_DEV(0, 0x1f, 0)
@ -100,12 +98,7 @@ void mainboard_romstage_entry(unsigned long bist)
if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET)
boot_path = BOOT_PATH_WARM_RESET; boot_path = BOOT_PATH_WARM_RESET;
printk(BIOS_DEBUG, "Initializing memory\n");
timestamp_add_now(TS_BEFORE_INITRAM);
sdram_initialize(boot_path, spd_addrmap); sdram_initialize(boot_path, spd_addrmap);
timestamp_add_now(TS_AFTER_INITRAM);
quick_ram_check();
printk(BIOS_DEBUG, "Memory initialized\n");
x4x_late_init(s3_resume); x4x_late_init(s3_resume);

7
src/mainboard/intel/dg43gt/romstage.c
View File

@ -23,9 +23,7 @@
#include <cpu/intel/romstage.h> #include <cpu/intel/romstage.h>
#include <superio/winbond/w83627dhg/w83627dhg.h> #include <superio/winbond/w83627dhg/w83627dhg.h>
#include <superio/winbond/common/winbond.h> #include <superio/winbond/common/winbond.h>
#include <lib.h>
#include <northbridge/intel/x4x/iomap.h> #include <northbridge/intel/x4x/iomap.h>
#include <timestamp.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
#define LPC_DEV PCI_DEV(0, 0x1f, 0) #define LPC_DEV PCI_DEV(0, 0x1f, 0)
@ -93,12 +91,7 @@ void mainboard_romstage_entry(unsigned long bist)
if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET)
boot_path = BOOT_PATH_WARM_RESET; boot_path = BOOT_PATH_WARM_RESET;
printk(BIOS_DEBUG, "Initializing memory\n");
timestamp_add_now(TS_BEFORE_INITRAM);
sdram_initialize(boot_path, spd_addrmap); sdram_initialize(boot_path, spd_addrmap);
timestamp_add_now(TS_AFTER_INITRAM);
quick_ram_check();
printk(BIOS_DEBUG, "Memory initialized\n");
x4x_late_init(s3_resume); x4x_late_init(s3_resume);

7
src/mainboard/lenovo/thinkcentre_a58/romstage.c
View File

@ -22,10 +22,8 @@
#include <cpu/x86/bist.h> #include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h> #include <cpu/intel/romstage.h>
#include <superio/smsc/smscsuperio/smscsuperio.h> #include <superio/smsc/smscsuperio/smscsuperio.h>
#include <lib.h>
#include <northbridge/intel/x4x/iomap.h> #include <northbridge/intel/x4x/iomap.h>
#include <device/pnp_def.h> #include <device/pnp_def.h>
#include <timestamp.h>
#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
#define LPC_DEV PCI_DEV(0, 0x1f, 0) #define LPC_DEV PCI_DEV(0, 0x1f, 0)
@ -86,12 +84,7 @@ void mainboard_romstage_entry(unsigned long bist)
if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET)
boot_path = BOOT_PATH_WARM_RESET; boot_path = BOOT_PATH_WARM_RESET;
printk(BIOS_DEBUG, "Initializing memory\n");
timestamp_add_now(TS_BEFORE_INITRAM);
sdram_initialize(boot_path, spd_addrmap); sdram_initialize(boot_path, spd_addrmap);
timestamp_add_now(TS_AFTER_INITRAM);
quick_ram_check();
printk(BIOS_DEBUG, "Memory initialized\n");
x4x_late_init(s3_resume); x4x_late_init(s3_resume);

7
src/northbridge/intel/x4x/raminit.c
View File

@ -22,6 +22,7 @@
#include <arch/cpu.h> #include <arch/cpu.h>
#include <delay.h> #include <delay.h>
#include <halt.h> #include <halt.h>
#include <lib.h>
#include "iomap.h" #include "iomap.h"
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) #if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)
#include <southbridge/intel/i82801gx/i82801gx.h> /* smbus_read_byte */ #include <southbridge/intel/i82801gx/i82801gx.h> /* smbus_read_byte */
@ -34,6 +35,7 @@
#include <device/dram/ddr2.h> #include <device/dram/ddr2.h>
#include <device/dram/ddr3.h> #include <device/dram/ddr3.h>
#include <mrc_cache.h> #include <mrc_cache.h>
#include <timestamp.h>
#define MRC_CACHE_VERSION 0 #define MRC_CACHE_VERSION 0
@ -639,6 +641,7 @@ void sdram_initialize(int boot_path, const u8 *spd_map)
int fast_boot, cbmem_was_inited, cache_not_found; int fast_boot, cbmem_was_inited, cache_not_found;
struct region_device rdev; struct region_device rdev;
timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "Setting up RAM controller.\n"); printk(BIOS_DEBUG, "Setting up RAM controller.\n");
pci_write_config8(PCI_DEV(0, 0, 0), 0xdf, 0xff); pci_write_config8(PCI_DEV(0, 0, 0), 0xdf, 0xff);
@ -728,4 +731,8 @@ void sdram_initialize(int boot_path, const u8 *spd_map)
outb(0x6, 0xcf9); outb(0x6, 0xcf9);
halt(); halt();
} }
timestamp_add_now(TS_AFTER_INITRAM);
quick_ram_check();
printk(BIOS_DEBUG, "Memory initialized\n");
} }