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mb/intel/jslrvp: Correct PCI root port mapping 

Jasper Lake SoC had PCI root port mapping swap, thats why we were
using swapped mapping earlier for all the boards

Recently, patch was pushed to handle this swap in PCI enumeration code
for Jasper Lake and we need to correct this mapping. Now this mapping
aligns with actual port mapping in the schematics

BUG=None
BRANCH=None
TEST=NVMe and WLAN are getting detected after this changes

Change-Id: Ide5f8419a15f559cefeb6039f155fabf97c279f8
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This commit is contained in:
Maulik V Vaghela 2020-08-11 18:28:29 +05:30 committed by Subrata Banik
parent bf4e71e1b3
commit f5b3a49b76
1 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
View File

@ -416,12 +416,12 @@ chip soc/intel/jasperlake
device pci 19.2 on end # UART #2
device pci 1a.0 on end # eMMC
device pci 1c.0 on end # PCI Express Port 1
device pci 1c.1 off end # PCI Express Port 2
device pci 1c.0 off end # PCI Express Port 1
device pci 1c.1 on end # PCI Express Port 2 - WLAN
device pci 1c.2 off end # PCI Express Port 3
device pci 1c.3 off end # PCI Express Port 4
device pci 1c.4 off end # PCI Express Port 5
device pci 1c.5 on end # PCI Express Port 6
device pci 1c.4 on end # PCI Express Port 5 - NVMe
device pci 1c.5 off end # PCI Express Port 6
device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 off end # PCI Express Port 8
device pci 1e.0 on end # UART #0