diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index da125b49a0..cd86e83120 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -95,7 +95,7 @@ typedef struct acpi_rsdp { char signature[8]; /* RSDP signature */ u8 checksum; /* Checksum of the first 20 bytes */ char oem_id[6]; /* OEM ID */ - u8 revision; /* 0 for ACPI 1.0, 2 for ACPI 2.0/3.0/4.0 */ + u8 revision; /* 0 for ACPI 1.0, 2 for ACPI 2.0/3.0/4.0/6.2a */ u32 rsdt_address; /* Physical address of RSDT (32 bits) */ u32 length; /* Total RSDP length (incl. extended part) */ u64 xsdt_address; /* Physical address of XSDT (64 bits) */ @@ -111,7 +111,8 @@ typedef struct acpi_gen_regaddr { u8 bit_offset; /* Register bit offset */ union { u8 resv; /* Reserved in ACPI 2.0 - 2.0b */ - u8 access_size; /* Access size in ACPI 2.0c/3.0/4.0/5.0 + u8 access_size; /* Access size in + * ACPI 2.0c/3.0/4.0/5.0/6.2a */ }; u32 addrl; /* Register address, low 32 bits */ @@ -229,7 +230,7 @@ typedef struct acpi_srat_lapic { u32 flags; /* Enable bit 0 = 1, other bits reserved to 0 */ u8 local_sapic_eid; /* Local SAPIC EID */ u8 proximity_domain_31_8[3]; /* Proximity domain bits[31:8] */ - u32 resv; /* TODO: Clock domain in ACPI 4.0. */ + u32 clock_domain; /* _CDM Clock Domain */ } __packed acpi_srat_lapic_t; /* SRAT: Memory Affinity Structure */ @@ -316,7 +317,8 @@ enum dev_scope_type { SCOPE_PCI_ENDPOINT = 1, SCOPE_PCI_SUB = 2, SCOPE_IOAPIC = 3, - SCOPE_MSI_HPET = 4 + SCOPE_MSI_HPET = 4, + SCOPE_ACPI_NAMESPACE_DEVICE = 5 }; typedef struct dev_scope { @@ -335,7 +337,8 @@ enum dmar_type { DMAR_DRHD = 0, DMAR_RMRR = 1, DMAR_ATSR = 2, - DMAR_RHSA = 3 + DMAR_RHSA = 3, + DMAR_ANDD = 4 }; enum { @@ -343,8 +346,9 @@ enum { }; enum dmar_flags { - DMAR_INTR_REMAP = 1, - DMAR_X2APIC_OPT_OUT = 2, + DMAR_INTR_REMAP = 1, + DMAR_X2APIC_OPT_OUT = 2, + DMA_CTRL_PLATFORM_OPT_IN_FLAG = 3, }; typedef struct dmar_entry { @@ -396,7 +400,12 @@ enum acpi_apic_types { PlatformIRQSources = 8, /* Platform interrupt sources */ Localx2Apic = 9, /* Processor local x2APIC */ Localx2ApicNMI = 10, /* Local x2APIC NMI */ - /* 0x0b-0x7f: Reserved */ + GICC = 11, /* GIC CPU Interface */ + GICD = 12, /* GIC Distributor */ + GIC_MSI_FRAME = 13, /* GIC MSI Frame */ + GICR = 14, /* GIC Redistributor */ + GIC_ITS = 15, /* Interrupt Translation Service */ + /* 0x10-0x7f: Reserved */ /* 0x80-0xff: Reserved for OEM use */ }; @@ -480,7 +489,11 @@ typedef struct acpi_fadt { struct acpi_table_header header; u32 firmware_ctrl; u32 dsdt; - u8 model; + u8 model; /* Eliminated in ACPI 2.0. Platforms should set + * this field to zero but field values of one + * are also allowed to maintain compatibility + * with ACPI 1.0. + */ u8 preferred_pm_profile; u16 sci_int; u32 smi_cmd; @@ -518,9 +531,8 @@ typedef struct acpi_fadt { u32 flags; struct acpi_gen_regaddr reset_reg; u8 reset_value; - u8 res3; - u8 res4; - u8 res5; + u16 ARM_boot_arch; + u8 FADT_MinorVersion; u32 x_firmware_ctl_l; u32 x_firmware_ctl_h; u32 x_dsdt_l; @@ -541,6 +553,7 @@ typedef struct acpi_fadt { #define ACPI_FADT_REV_ACPI_3_0 4 #define ACPI_FADT_REV_ACPI_4_0 4 #define ACPI_FADT_REV_ACPI_5_0 5 +#define ACPI_FADT_REV_ACPI_6_0 6 /* Flags for p_lvl2_lat and p_lvl3_lat */ #define ACPI_FADT_C2_NOT_SUPPORTED 101 @@ -570,7 +583,7 @@ typedef struct acpi_fadt { /* Bits 20-31: reserved ACPI 3.0 & 4.0 */ #define ACPI_FADT_HW_REDUCED_ACPI (1 << 20) #define ACPI_FADT_LOW_PWR_IDLE_S0 (1 << 21) -/* bits 22-31: reserved ACPI 5.0 */ +/* bits 22-31: reserved ACPI 5.0/6.2a */ /* FADT Boot Architecture Flags */ #define ACPI_FADT_LEGACY_DEVICES (1 << 0) @@ -578,8 +591,14 @@ typedef struct acpi_fadt { #define ACPI_FADT_VGA_NOT_PRESENT (1 << 2) #define ACPI_FADT_MSI_NOT_SUPPORTED (1 << 3) #define ACPI_FADT_NO_PCIE_ASPM_CONTROL (1 << 4) +#define ACPI_FADT_NO_CMOS_RTC (1 << 5) #define ACPI_FADT_LEGACY_FREE 0x00 /* No legacy devices (including 8042) */ +/* FADT ARM Boot Architecture Flags */ +#define ACPI_FADT_ARM_PSCI_COMPLIANT (1 << 0) +#define ACPI_FADT_ARM_PSCI_USE_HVC (1 << 1) +/* bits 2-16: reserved ACPI 6.2a */ + /* FADT Preferred Power Management Profile */ enum acpi_preferred_pm_profiles { PM_UNSPECIFIED = 0, @@ -590,7 +609,7 @@ enum acpi_preferred_pm_profiles { PM_SOHO_SERVER = 5, PM_APPLIANCE_PC = 6, PM_PERFORMANCE_SERVER = 7, - PM_TABLET = 8, /* ACPI 5.0 */ + PM_TABLET = 8, /* ACPI 5.0/6.2a */ }; /* FACS (Firmware ACPI Control Structure) */ @@ -603,8 +622,10 @@ typedef struct acpi_facs { u32 flags; /* FACS flags */ u32 x_firmware_waking_vector_l; /* X FW waking vector, low */ u32 x_firmware_waking_vector_h; /* X FW waking vector, high */ - u8 version; /* ACPI 4.0: 2 */ - u8 resv[31]; /* FIXME: 4.0: ospm_flags */ + u8 version; /* ACPI 6.2-A: 2 */ + u8 resv1[3]; /* ACPI 6.2-A: 0 */ + u32 ospm_flags; /* 64BIT_WAKE_F */ + u8 resv2[24]; /* ACPI 6.2-A: 0 */ } __packed acpi_facs_t; /* FACS flags */ diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index 1f6e62abb7..645aff4531 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -159,9 +159,8 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) fadt->reset_value = 6; - fadt->res3 = 0; /* reserved, MUST be 0 ACPI 3.0 */ - fadt->res4 = 0; /* reserved, MUST be 0 ACPI 3.0 */ - fadt->res5 = 0; /* reserved, MUST be 0 ACPI 3.0 */ + fadt->ARM_boot_arch = 0; /* MUST be 0 ACPI 3.0 */ + fadt->FADT_MinorVersion = 0; /* MUST be 0 ACPI 3.0 */ fadt->x_firmware_ctl_l = 0; /* set to 0 if firmware_ctrl is used */ fadt->x_firmware_ctl_h = 0; diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c index a378f5e7c6..2640a80daf 100644 --- a/src/soc/intel/fsp_baytrail/acpi.c +++ b/src/soc/intel/fsp_baytrail/acpi.c @@ -258,10 +258,8 @@ void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->reset_reg.addrh = 0x00; fadt->reset_value = 6; - /* Reserved Bits */ - fadt->res3 = 0x00; /* reserved, MUST be 0 ACPI 3.0 */ - fadt->res4 = 0x00; /* reserved, MUST be 0 ACPI 3.0 */ - fadt->res5 = 0x00; /* reserved, MUST be 0 ACPI 3.0 */ + fadt->ARM_boot_arch = 0; /* MUST be 0 ACPI 3.0 */ + fadt->FADT_MinorVersion = 0; /* MUST be 0 ACPI 3.0 */ /* Extended ACPI Pointers */ fadt->x_firmware_ctl_l = (unsigned long)facs; diff --git a/src/soc/intel/fsp_broadwell_de/acpi.c b/src/soc/intel/fsp_broadwell_de/acpi.c index 15ea5eccea..d5bee64a24 100644 --- a/src/soc/intel/fsp_broadwell_de/acpi.c +++ b/src/soc/intel/fsp_broadwell_de/acpi.c @@ -238,10 +238,8 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) fadt->reset_reg.addrh = 0x00; fadt->reset_value = 6; - /* Reserved Bits */ - fadt->res3 = 0x00; /* reserved, MUST be 0 ACPI 3.0 */ - fadt->res4 = 0x00; /* reserved, MUST be 0 ACPI 3.0 */ - fadt->res5 = 0x00; /* reserved, MUST be 0 ACPI 3.0 */ + fadt->ARM_boot_arch = 0; /* MUST be 0 ACPI 3.0 */ + fadt->FADT_MinorVersion = 0; /* MUST be 0 ACPI 3.0 */ /* Extended ACPI Pointers */ fadt->x_firmware_ctl_l = (unsigned long)facs; diff --git a/src/southbridge/amd/agesa/hudson/fadt.c b/src/southbridge/amd/agesa/hudson/fadt.c index 1cb9875d10..e8483a045c 100644 --- a/src/southbridge/amd/agesa/hudson/fadt.c +++ b/src/southbridge/amd/agesa/hudson/fadt.c @@ -138,10 +138,8 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->reset_value = 6; - fadt->res3 = 0; /* reserved, MUST be 0 ACPI 3.0 */ - fadt->res4 = 0; /* reserved, MUST be 0 ACPI 3.0 */ - fadt->res5 = 0; /* reserved, MUST be 0 ACPI 3.0 */ - + fadt->ARM_boot_arch = 0; /* MUST be 0 ACPI 3.0 */ + fadt->FADT_MinorVersion = 0; /* MUST be 0 ACPI 3.0 */ fadt->x_firmware_ctl_l = ((uintptr_t)facs) & 0xffffffff; fadt->x_firmware_ctl_h = ((uint64_t)(uintptr_t)facs) >> 32; diff --git a/src/southbridge/amd/cimx/sb800/fadt.c b/src/southbridge/amd/cimx/sb800/fadt.c index 59e61da252..15e05c398e 100644 --- a/src/southbridge/amd/cimx/sb800/fadt.c +++ b/src/southbridge/amd/cimx/sb800/fadt.c @@ -153,9 +153,8 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->reset_reg.addrh = 0x0; fadt->reset_value = 6; - fadt->res3 = 0; /* reserved, MUST be 0 ACPI 3.0 */ - fadt->res4 = 0; /* reserved, MUST be 0 ACPI 3.0 */ - fadt->res5 = 0; /* reserved, MUST be 0 ACPI 3.0 */ + fadt->ARM_boot_arch = 0; /* MUST be 0 ACPI 3.0 */ + fadt->FADT_MinorVersion = 0; /* MUST be 0 ACPI 3.0 */ fadt->x_firmware_ctl_l = ((uintptr_t)facs) & 0xffffffff; fadt->x_firmware_ctl_h = ((uint64_t)(uintptr_t)facs) >> 32; diff --git a/src/southbridge/amd/pi/hudson/fadt.c b/src/southbridge/amd/pi/hudson/fadt.c index c2a3ff4a46..c2d5d19ddb 100644 --- a/src/southbridge/amd/pi/hudson/fadt.c +++ b/src/southbridge/amd/pi/hudson/fadt.c @@ -130,9 +130,8 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->reset_value = 6; - fadt->res3 = 0; /* reserved, MUST be 0 ACPI 3.0 */ - fadt->res4 = 0; /* reserved, MUST be 0 ACPI 3.0 */ - fadt->res5 = 0; /* reserved, MUST be 0 ACPI 3.0 */ + fadt->ARM_boot_arch = 0; /* MUST be 0 ACPI 3.0 */ + fadt->FADT_MinorVersion = 0; /* MUST be 0 ACPI 3.0 */ fadt->x_firmware_ctl_l = 0; /* set to 0 if firmware_ctrl is used */ fadt->x_firmware_ctl_h = 0; diff --git a/src/southbridge/intel/fsp_rangeley/acpi.c b/src/southbridge/intel/fsp_rangeley/acpi.c index ca711dce24..efe5412c9f 100644 --- a/src/southbridge/intel/fsp_rangeley/acpi.c +++ b/src/southbridge/intel/fsp_rangeley/acpi.c @@ -120,10 +120,8 @@ void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->reset_reg.addrh = 0x00; fadt->reset_value = 6; - /* Reserved Bits */ - fadt->res3 = 0x00; /* reserved, MUST be 0 ACPI 3.0 */ - fadt->res4 = 0x00; /* reserved, MUST be 0 ACPI 3.0 */ - fadt->res5 = 0x00; /* reserved, MUST be 0 ACPI 3.0 */ + fadt->ARM_boot_arch = 0; /* MUST be 0 ACPI 3.0 */ + fadt->FADT_MinorVersion = 0; /* MUST be 0 ACPI 3.0 */ /* Extended ACPI Pointers */ fadt->x_firmware_ctl_l = (unsigned long)facs;