Move calls to quick_ram_check() before CBMEM init
After raminit completes, do a read-modify-write test just below CBMEM top address. If test fails, die(). Change-Id: I33d4153a5ce0908b8889517394afb46f1ca28f92 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31978 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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@ -20,7 +20,6 @@
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#include <cpu/x86/bist.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/mtrr.h>
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#include <lib.h>
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#include <timestamp.h>
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#include <device/pci_def.h>
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#include <cpu/x86/lapic.h>
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@ -121,9 +120,6 @@ void romstage_common(const struct romstage_params *params)
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intel_early_me_status();
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quick_ram_check();
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post_code(0x3e);
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if (!wake_from_s3) {
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cbmem_initialize_empty();
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/* Save data returned from MRC on non-S3 resumes. */
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@ -24,10 +24,11 @@
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size_t ulzman(const void *src, size_t srcn, void *dst, size_t dstn);
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/* Defined in src/lib/ramtest.c */
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/* Assumption is 32-bit addressable UC memory. */
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void ram_check(unsigned long start, unsigned long stop);
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int ram_check_nodie(unsigned long start, unsigned long stop);
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int ram_check_noprint_nodie(unsigned long start, unsigned long stop);
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void quick_ram_check(void);
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void quick_ram_check_or_die(uintptr_t dst);
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/* Defined in primitive_memtest.c */
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int primitive_memtest(uintptr_t base, uintptr_t size);
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@ -18,6 +18,7 @@
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#include <console/console.h>
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#include <cbmem.h>
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#include <imd.h>
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#include <lib.h>
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#include <stdlib.h>
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#include <arch/early_variables.h>
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@ -119,6 +120,10 @@ static void cbmem_top_init_once(void)
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return;
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cbmem_top_init();
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/* The test is only effective on X86 and when address hits UC memory. */
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if (ENV_X86)
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quick_ram_check_or_die((uintptr_t)cbmem_top() - sizeof(u32));
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}
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void cbmem_initialize_empty_id_size(u32 id, u64 size)
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@ -171,7 +171,10 @@ int ram_check_noprint_nodie(unsigned long start, unsigned long stop)
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return failures;
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}
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static void __quick_ram_check(uintptr_t dst)
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/* Assumption is 32-bit addressable UC memory at dst. This also executes
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* on S3 resume path so target memory must be restored.
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*/
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void quick_ram_check_or_die(uintptr_t dst)
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{
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int fail = 0;
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u32 backup;
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@ -200,8 +203,3 @@ static void __quick_ram_check(uintptr_t dst)
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}
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phys_memory_barrier();
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}
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void quick_ram_check(void)
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{
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__quick_ram_check(0x100000);
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}
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@ -23,7 +23,6 @@
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#include <device/pci_ops.h>
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#include <device/pci_def.h>
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#include <cpu/x86/lapic.h>
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#include <lib.h>
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#include <romstage_handoff.h>
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#include <console/console.h>
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#include <cpu/x86/bist.h>
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@ -273,7 +272,4 @@ void mainboard_romstage_entry(unsigned long bist)
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}
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romstage_handoff_init(s3resume);
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if (!s3resume)
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quick_ram_check();
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}
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@ -23,7 +23,6 @@
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#include <device/pci_ops.h>
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#include <device/pci_def.h>
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#include <cpu/x86/lapic.h>
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#include <lib.h>
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#include <romstage_handoff.h>
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#include <console/console.h>
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#include <cpu/x86/bist.h>
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@ -266,7 +265,4 @@ void mainboard_romstage_entry(unsigned long bist)
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}
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romstage_handoff_init(s3resume);
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if (!s3resume)
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quick_ram_check();
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}
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@ -18,7 +18,6 @@
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*/
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#include <arch/io.h>
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#include <lib.h>
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#include <timestamp.h>
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#include <console/console.h>
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#include <device/pci_ops.h>
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@ -105,8 +104,6 @@ void mainboard_romstage_entry(unsigned long bist)
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post_code(0x31);
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quick_ram_check();
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mb_pirq_setup();
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rcba_config();
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@ -31,7 +31,6 @@
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#include <southbridge/intel/common/smbus.h>
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#include <cpu/x86/msr.h>
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#include <delay.h>
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#include <lib.h>
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#include "raminit_native.h"
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#include "raminit_common.h"
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#include "sandybridge.h"
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@ -419,9 +418,6 @@ static void init_dram_ddr3(int min_tck, int s3resume)
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/* Zone config */
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dram_zones(&ctrl, 0);
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/* Non intrusive, fast ram check */
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quick_ram_check();
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intel_early_me_status();
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intel_early_me_init_done(ME_INIT_STATUS_SUCCESS);
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intel_early_me_status();
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@ -23,7 +23,6 @@
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#include <arch/cpu.h>
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#include <delay.h>
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#include <halt.h>
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#include <lib.h>
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#include "iomap.h"
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#if CONFIG(SOUTHBRIDGE_INTEL_I82801GX)
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#include <southbridge/intel/i82801gx/i82801gx.h> /* smbus_read_byte */
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@ -734,6 +733,5 @@ void sdram_initialize(int boot_path, const u8 *spd_map)
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}
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timestamp_add_now(TS_AFTER_INITRAM);
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quick_ram_check();
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printk(BIOS_DEBUG, "Memory initialized\n");
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}
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@ -20,7 +20,6 @@
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#include <cf9_reset.h>
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#include <console/console.h>
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#include <device/pci_def.h>
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#include <lib.h>
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#include <memory_info.h>
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#include <mrc_cache.h>
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#include <string.h>
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@ -98,9 +97,6 @@ void raminit(struct pei_data *pei_data)
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report_memory_config();
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/* Basic memory sanity test */
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quick_ram_check();
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if (pei_data->boot_mode != ACPI_S3) {
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cbmem_initialize_empty();
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} else if (cbmem_initialize()) {
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@ -15,7 +15,6 @@
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*/
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#include <stddef.h>
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#include <lib.h>
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#include <arch/io.h>
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#include <device/mmio.h>
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#include <device/pci_ops.h>
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@ -245,12 +244,6 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr)
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late_mainboard_romstage_entry();
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post_code(0x4c);
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/* if S3 resume skip RAM check */
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if (prev_sleep_state != ACPI_S3) {
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quick_ram_check();
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post_code(0x4d);
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}
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cbmem_was_initted = !cbmem_recovery(prev_sleep_state == ACPI_S3);
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/* Save the HOB pointer in CBMEM to be used in ramstage*/
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@ -16,7 +16,6 @@
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*/
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#include <stddef.h>
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#include <lib.h>
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#include <device/pci_ops.h>
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#include <arch/cbfs.h>
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#include <cbmem.h>
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@ -112,9 +111,6 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr)
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post_code(0x4b);
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late_mainboard_romstage_entry();
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post_code(0x4c);
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quick_ram_check();
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post_code(0x4d);
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cbmem_was_initted = !cbmem_recovery(0);
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@ -15,7 +15,6 @@
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*/
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#include <stdint.h>
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#include <lib.h>
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#include <timestamp.h>
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#include <arch/io.h>
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#include <device/mmio.h>
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@ -114,9 +113,6 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
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/* Decode E0000 and F0000 segment to DRAM */
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sideband_write(B_UNIT, BMISC, sideband_read(B_UNIT, BMISC) | (1 << 1) | (1 << 0));
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quick_ram_check();
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post_code(0x4d);
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cbmem_was_initted = !cbmem_recovery(0);
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/* Save the HOB pointer in CBMEM to be used in ramstage*/
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