GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

{cpu,nb}/intel/haswell: Drop unnecessary `UL` suffix 

Tested with BUILD_TIMELESS=1, Google Wolf does not change.

Change-Id: I029ab0dccbf7b61d641cccf79b491fabf97ab74a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46720
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-10-24 12:24:19 +02:00 committed by Michael Niewöhner
parent 8963f7d40b
commit f5dd7b6eb9
4 changed files with 8 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/cpu/intel/haswell/haswell.h
View File

@ -84,7 +84,7 @@
/* PCODE MMIO communications live in the MCHBAR. */
#define BIOS_MAILBOX_INTERFACE 0x5da4
#define MAILBOX_RUN_BUSY (1UL << 31)
#define MAILBOX_RUN_BUSY (1 << 31)
#define MAILBOX_BIOS_CMD_READ_PCS 1
#define MAILBOX_BIOS_CMD_WRITE_PCS 2
#define MAILBOX_BIOS_CMD_READ_CALIBRATION 0x509

4
src/northbridge/intel/haswell/finalize.c
View File

@ -22,10 +22,10 @@ void intel_northbridge_haswell_finalize_smm(void)
MCHBAR32_OR(MMIO_PAVP_MSG, 1 << 0); /* PAVP */
MCHBAR32_OR(PCU_DDR_PTM_CTL, 1 << 5); /* DDR PTM */
MCHBAR32_OR(DMIVCLIM, 1UL << 31);
MCHBAR32_OR(DMIVCLIM, 1 << 31);
MCHBAR32_OR(CRDTLCK, 1 << 0);
MCHBAR32_OR(MCARBLCK, 1 << 0);
MCHBAR32_OR(REQLIM, 1UL << 31);
MCHBAR32_OR(REQLIM, 1 << 31);
MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */
MCHBAR32_OR(VTDTRKLCK, 1 << 0); /* VTDTRK */

4
src/northbridge/intel/haswell/gma.c
View File

@ -196,7 +196,7 @@ static void gma_pm_init_pre_vbios(struct device *dev)
gtt_write_regs(haswell_gt_setup);
/* Wait for Mailbox Ready */
gtt_poll(0x138124, (1UL << 31), (0UL << 31));
gtt_poll(0x138124, (1 << 31), (0 << 31));
/* Mailbox Data - RC6 VIDS */
gtt_write(0x138128, 0x00000000);
@ -205,7 +205,7 @@ static void gma_pm_init_pre_vbios(struct device *dev)
gtt_write(0x138124, 0x80000004);
/* Wait for Mailbox Ready */
gtt_poll(0x138124, (1UL << 31), (0UL << 31));
gtt_poll(0x138124, (1 << 31), (0 << 31));
/* Enable PM Interrupts */
gtt_write(GEN6_PMIER, GEN6_PM_MBOX_EVENT | GEN6_PM_THERMAL_EVENT |

6
src/northbridge/intel/haswell/northbridge.c
View File

@ -31,18 +31,18 @@ static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 *
switch ((pciexbar_reg >> 1) & 3) {
case 0: /* 256MB */
mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28);
mask = (1 << 31) | (1 << 30) | (1 << 29) | (1 << 28);
*base = pciexbar_reg & mask;
*len = 256 * 1024 * 1024;
return 1;
case 1: /* 128M */
mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28);
mask = (1 << 31) | (1 << 30) | (1 << 29) | (1 << 28);
mask |= (1 << 27);
*base = pciexbar_reg & mask;
*len = 128 * 1024 * 1024;
return 1;
case 2: /* 64M */
mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28);
mask = (1 << 31) | (1 << 30) | (1 << 29) | (1 << 28);
mask |= (1 << 27) | (1 << 26);
*base = pciexbar_reg & mask;
*len = 64 * 1024 * 1024;