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AMD amdfam10: Always have HT3_SUPPORT 

Change-Id: I6ce784fd9e7a6876a37c910c503fafa3a17bf96f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8348
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Kyösti Mälkki 2015-02-04 13:49:07 +02:00
parent 260a6db7ec
commit f5e7fa22e7
7 changed files with 4 additions and 25 deletions
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1
src/cpu/amd/socket_AM2r2/Kconfig
View File

@ -1,7 +1,6 @@
config CPU_AMD_SOCKET_AM2R2
bool
select CPU_AMD_MODEL_10XXX
select HT3_SUPPORT
select PCI_IO_CFG_EXT
select X86_AMD_FIXED_MTRRS

1
src/cpu/amd/socket_AM3/Kconfig
View File

@ -1,7 +1,6 @@
config CPU_AMD_SOCKET_AM3
bool
select CPU_AMD_MODEL_10XXX
select HT3_SUPPORT
select PCI_IO_CFG_EXT
select X86_AMD_FIXED_MTRRS

1
src/cpu/amd/socket_ASB2/Kconfig
View File

@ -1,7 +1,6 @@
config CPU_AMD_SOCKET_ASB2
bool
select CPU_AMD_MODEL_10XXX
select HT3_SUPPORT
select PCI_IO_CFG_EXT
select X86_AMD_FIXED_MTRRS

1
src/cpu/amd/socket_C32/Kconfig
View File

@ -1,7 +1,6 @@
config CPU_AMD_SOCKET_C32_NON_AGESA
bool
select CPU_AMD_MODEL_10XXX
select HT3_SUPPORT
select PCI_IO_CFG_EXT
select X86_AMD_FIXED_MTRRS

4
src/mainboard/msi/ms9652_fam10/Kconfig
View File

@ -89,10 +89,6 @@ config APIC_ID_OFFSET
hex
default 0x00
config HT3_SUPPORT
bool
default y
config MCP55_PCI_E_X_0
int
default 1

4
src/northbridge/amd/amdfam10/Kconfig
View File

@ -33,10 +33,6 @@ config AGP_APERTURE_SIZE
hex
default 0x4000000
config HT3_SUPPORT
bool
default y
config AMDMCT
bool
default y

17
src/northbridge/amd/amdfam10/northbridge.c
View File

@ -152,7 +152,6 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 s
u32 ht_unitid_base[4]; // here assume only 4 HT device on chain
u32 max_bus;
u32 min_bus;
u32 is_sublink1 = (link->link_num > 3);
device_t devx;
u32 busses;
u32 segn = max>>8;
@ -161,18 +160,16 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 s
#endif
u32 max_devfn;
#if CONFIG_HT3_SUPPORT
if(is_sublink1) {
if (link->link_num > 3) {
u32 regpos;
u32 reg;
regpos = 0x170 + 4 * (link->link_num & 3); // it is only on sublink0
reg = pci_read_config32(dev, regpos);
if(reg & 1) return max; // already ganged no sblink1
devx = get_node_pci(nodeid, 4);
} else
#endif
} else {
devx = dev;
}
link->cap = 0x80 + ((link->link_num & 3) * 0x20);
do {
@ -1322,13 +1319,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
/* Ok, We need to set the links for that device.
* otherwise the device under it will not be scanned
*/
int linknum;
#if CONFIG_HT3_SUPPORT
linknum = 8;
#else
linknum = 4;
#endif
add_more_links(cdb_dev, linknum);
add_more_links(cdb_dev, 8);
}
cores_found = 0; // one core