AMD amdfam10: Always have HT3_SUPPORT
Change-Id: I6ce784fd9e7a6876a37c910c503fafa3a17bf96f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8348 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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@ -1,7 +1,6 @@
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config CPU_AMD_SOCKET_AM2R2
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config CPU_AMD_SOCKET_AM2R2
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bool
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bool
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select CPU_AMD_MODEL_10XXX
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select CPU_AMD_MODEL_10XXX
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select HT3_SUPPORT
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select PCI_IO_CFG_EXT
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select PCI_IO_CFG_EXT
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select X86_AMD_FIXED_MTRRS
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select X86_AMD_FIXED_MTRRS
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@ -1,7 +1,6 @@
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config CPU_AMD_SOCKET_AM3
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config CPU_AMD_SOCKET_AM3
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bool
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bool
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select CPU_AMD_MODEL_10XXX
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select CPU_AMD_MODEL_10XXX
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select HT3_SUPPORT
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select PCI_IO_CFG_EXT
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select PCI_IO_CFG_EXT
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select X86_AMD_FIXED_MTRRS
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select X86_AMD_FIXED_MTRRS
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@ -1,7 +1,6 @@
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config CPU_AMD_SOCKET_ASB2
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config CPU_AMD_SOCKET_ASB2
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bool
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bool
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select CPU_AMD_MODEL_10XXX
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select CPU_AMD_MODEL_10XXX
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select HT3_SUPPORT
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select PCI_IO_CFG_EXT
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select PCI_IO_CFG_EXT
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select X86_AMD_FIXED_MTRRS
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select X86_AMD_FIXED_MTRRS
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@ -1,7 +1,6 @@
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config CPU_AMD_SOCKET_C32_NON_AGESA
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config CPU_AMD_SOCKET_C32_NON_AGESA
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bool
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bool
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select CPU_AMD_MODEL_10XXX
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select CPU_AMD_MODEL_10XXX
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select HT3_SUPPORT
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select PCI_IO_CFG_EXT
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select PCI_IO_CFG_EXT
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select X86_AMD_FIXED_MTRRS
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select X86_AMD_FIXED_MTRRS
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@ -89,10 +89,6 @@ config APIC_ID_OFFSET
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hex
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hex
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default 0x00
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default 0x00
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config HT3_SUPPORT
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bool
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default y
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config MCP55_PCI_E_X_0
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config MCP55_PCI_E_X_0
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int
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int
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default 1
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default 1
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@ -33,10 +33,6 @@ config AGP_APERTURE_SIZE
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hex
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hex
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default 0x4000000
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default 0x4000000
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config HT3_SUPPORT
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bool
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default y
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config AMDMCT
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config AMDMCT
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bool
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bool
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default y
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default y
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@ -152,7 +152,6 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 s
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u32 ht_unitid_base[4]; // here assume only 4 HT device on chain
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u32 ht_unitid_base[4]; // here assume only 4 HT device on chain
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u32 max_bus;
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u32 max_bus;
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u32 min_bus;
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u32 min_bus;
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u32 is_sublink1 = (link->link_num > 3);
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device_t devx;
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device_t devx;
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u32 busses;
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u32 busses;
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u32 segn = max>>8;
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u32 segn = max>>8;
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@ -161,18 +160,16 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 s
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#endif
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#endif
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u32 max_devfn;
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u32 max_devfn;
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#if CONFIG_HT3_SUPPORT
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if (link->link_num > 3) {
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if(is_sublink1) {
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u32 regpos;
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u32 regpos;
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u32 reg;
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u32 reg;
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regpos = 0x170 + 4 * (link->link_num & 3); // it is only on sublink0
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regpos = 0x170 + 4 * (link->link_num & 3); // it is only on sublink0
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reg = pci_read_config32(dev, regpos);
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reg = pci_read_config32(dev, regpos);
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if(reg & 1) return max; // already ganged no sblink1
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if(reg & 1) return max; // already ganged no sblink1
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devx = get_node_pci(nodeid, 4);
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devx = get_node_pci(nodeid, 4);
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} else
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} else {
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#endif
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devx = dev;
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devx = dev;
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}
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link->cap = 0x80 + ((link->link_num & 3) * 0x20);
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link->cap = 0x80 + ((link->link_num & 3) * 0x20);
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do {
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do {
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@ -1322,13 +1319,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
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/* Ok, We need to set the links for that device.
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/* Ok, We need to set the links for that device.
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* otherwise the device under it will not be scanned
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* otherwise the device under it will not be scanned
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*/
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*/
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int linknum;
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add_more_links(cdb_dev, 8);
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#if CONFIG_HT3_SUPPORT
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linknum = 8;
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#else
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linknum = 4;
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#endif
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add_more_links(cdb_dev, linknum);
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}
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}
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cores_found = 0; // one core
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cores_found = 0; // one core
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