From f5ead3f029c9a7d1edfad171dd4df333491dc450 Mon Sep 17 00:00:00 2001
From: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Date: Fri, 4 Nov 2022 11:57:23 +0800
Subject: [PATCH] mb/google/brya/var/kinox: Disable PCH USB2 phy power gating

The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for kinox board. Please refer Intel doc#723158 for more
information.

BUG=b:257373738
TEST=Verify the build for kinox board

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Ifcf4f89ea4c61ec4f9a31edba069d2111ca06010
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
---
 src/mainboard/google/brya/variants/kinox/overridetree.cb | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/mainboard/google/brya/variants/kinox/overridetree.cb b/src/mainboard/google/brya/variants/kinox/overridetree.cb
index 8356320eaf..01610c12ba 100644
--- a/src/mainboard/google/brya/variants/kinox/overridetree.cb
+++ b/src/mainboard/google/brya/variants/kinox/overridetree.cb
@@ -12,6 +12,10 @@ chip soc/intel/alderlake
 	# GPE configuration
 	register "pmc_gpe0_dw1" = "GPP_H"
 
+	# As per Intel Advisory doc#723158, the change is required to prevent possible
+	# display flickering issue.
+	register "usb2_phy_sus_pg_disable" = "1"
+
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
 	#| Field             |  Value                    |