soc/intel: indicate to build system that XIP_ROM_SIZE isn't used

The XIP_ROM_SIZE Kconfig variable isn't used for these chipsets.
Therefore, indicate as such so that romstage can be placed in
cbfs less rigidly.

Change-Id: If5cae10b90e05029df56c282e8adf37fa0102955
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14626
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Aaron Durbin 2016-05-05 10:38:03 -05:00
parent ef10529187
commit f5ff854c36
4 changed files with 4 additions and 0 deletions

View File

@ -23,6 +23,7 @@ config CPU_SPECIFIC_OPTIONS
select HAVE_INTEL_FIRMWARE
select MMCONF_SUPPORT
select MMCONF_SUPPORT_DEFAULT
select NO_FIXED_XIP_ROM_SIZE
select PARALLEL_MP
select PCIEXP_ASPM
select PCIEXP_COMMON_CLOCK

View File

@ -18,6 +18,7 @@ config CPU_SPECIFIC_OPTIONS
select HAVE_HARD_RESET
select MMCONF_SUPPORT
select MMCONF_SUPPORT_DEFAULT
select NO_FIXED_XIP_ROM_SIZE
select RELOCATABLE_MODULES
select RELOCATABLE_RAMSTAGE
select PARALLEL_MP

View File

@ -21,6 +21,7 @@ config CPU_SPECIFIC_OPTIONS
select HAVE_HARD_RESET
select MMCONF_SUPPORT
select MMCONF_SUPPORT_DEFAULT
select NO_FIXED_XIP_ROM_SIZE
select RELOCATABLE_MODULES
select PARALLEL_MP
select PCIEXP_ASPM

View File

@ -24,6 +24,7 @@ config CPU_SPECIFIC_OPTIONS
select IOAPIC
select MMCONF_SUPPORT
select MMCONF_SUPPORT_DEFAULT
select NO_FIXED_XIP_ROM_SIZE
select PARALLEL_MP
select PCIEXP_ASPM
select PCIEXP_COMMON_CLOCK