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intelblocks/gpio: Add NAVFWE bit to PAD_CFG_DW0 mask definition 

Definition for NAV_FWE BIT was added in commit e6e8b3d

Even if try to set this BIT it was not getting set since PAD_CFG_DW0
mask will make it 0 since this bit was not part of mask.
Adding NAV_FWE to mask will resolve this issue and BIT will be set/unset
as per programming in mainboard.

TEST=Check GPIO register dump and see if BIT is getting set properly.

Change-Id: I970ae81ed36da45c3acc61814980b2e6ff889445
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54350
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Maulik V Vaghela 2021-05-17 12:25:40 +05:30 committed by Patrick Georgi
parent 71e7974784
commit f6004114ec
1 changed files with 1 additions and 1 deletions
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2
src/soc/intel/common/block/gpio/gpio.c
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@ -24,7 +24,7 @@
PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE | PAD_CFG0_MODE_MASK |\ PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE | PAD_CFG0_MODE_MASK |\
PAD_CFG0_ROUTE_MASK | PAD_CFG0_RXTENCFG_MASK | \ PAD_CFG0_ROUTE_MASK | PAD_CFG0_RXTENCFG_MASK | \
PAD_CFG0_RXINV_MASK | PAD_CFG0_PREGFRXSEL | \ PAD_CFG0_RXINV_MASK | PAD_CFG0_PREGFRXSEL | \
PAD_CFG0_TRIG_MASK | PAD_CFG0_RXRAW1_MASK | \ PAD_CFG0_TRIG_MASK | PAD_CFG0_RXRAW1_MASK | PAD_CFG0_NAFVWE_ENABLE |\
PAD_CFG0_RXPADSTSEL_MASK | PAD_CFG0_RESET_MASK) PAD_CFG0_RXPADSTSEL_MASK | PAD_CFG0_RESET_MASK)
#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL) #if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL)