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soc/intel/common: Include cometlake SA IDs 

Add cometlake specific SA IDs

Change-Id: I1fbbab8a7797b36a9eacbd1c6a0644466f2fe6b1
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/31226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
This commit is contained in:
Ronak Kanabar 2019-02-04 16:06:50 +05:30 committed by Subrata Banik
parent 128bb2a7ca
commit f606a2f5e6
4 changed files with 75 additions and 0 deletions
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25
src/include/device/pci_ids.h
View File

@ -3001,6 +3001,24 @@
#define PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_5 0x8A56
#define PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_6 0x8A57
#define PCI_DEVICE_ID_INTEL_ICL_GT3_ULT 0x8A62
#define PCI_DEVICE_ID_INTEL_CML_GT1_ULT_1 0x9B21
#define PCI_DEVICE_ID_INTEL_CML_GT1_ULT_2 0x9B2A
#define PCI_DEVICE_ID_INTEL_CML_GT2_ULT_1 0x9B41
#define PCI_DEVICE_ID_INTEL_CML_GT2_ULT_2 0x9B4A
#define PCI_DEVICE_ID_INTEL_CML_GT1_ULT_3 0x9B2B
#define PCI_DEVICE_ID_INTEL_CML_GT1_ULT_4 0x9B2C
#define PCI_DEVICE_ID_INTEL_CML_GT2_ULT_3 0x9B4B
#define PCI_DEVICE_ID_INTEL_CML_GT2_ULT_4 0x9B4C
#define PCI_DEVICE_ID_INTEL_CML_GT1_ULX_1 0x9B20
#define PCI_DEVICE_ID_INTEL_CML_GT2_ULX_1 0x9B40
#define PCI_DEVICE_ID_INTEL_CML_GT1_S_1 0x9B25
#define PCI_DEVICE_ID_INTEL_CML_GT1_S_2 0x9B28
#define PCI_DEVICE_ID_INTEL_CML_GT2_S_1 0x9B45
#define PCI_DEVICE_ID_INTEL_CML_GT2_S_2 0x9B48
#define PCI_DEVICE_ID_INTEL_CML_GT1_H_1 0x9B24
#define PCI_DEVICE_ID_INTEL_CML_GT1_H_2 0x9B22
#define PCI_DEVICE_ID_INTEL_CML_GT2_H_1 0x9B44
#define PCI_DEVICE_ID_INTEL_CML_GT2_H_2 0x9B42
/* Intel Northbridge Ids */
#define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0
@ -3027,6 +3045,13 @@
#define PCI_DEVICE_ID_INTEL_ICL_ID_U_2_2 0x8A02
#define PCI_DEVICE_ID_INTEL_ICL_ID_Y 0x8A10
#define PCI_DEVICE_ID_INTEL_ICL_ID_Y_2 0x8A00
#define PCI_DEVICE_ID_INTEL_CML_ULT 0x9B61
#define PCI_DEVICE_ID_INTEL_CML_ULT_6_2 0x9B51
#define PCI_DEVICE_ID_INTEL_CML_ULX 0x9B60
#define PCI_DEVICE_ID_INTEL_CML_S 0x9B55
#define PCI_DEVICE_ID_INTEL_CML_S_10_2 0x9B35
#define PCI_DEVICE_ID_INTEL_CML_H 0x9B54
#define PCI_DEVICE_ID_INTEL_CML_H_8_2 0x9B44
/* Intel SMBUS device Ids */
#define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS 0x9d23

25
src/soc/intel/cannonlake/bootblock/report_platform.c
View File

@ -57,6 +57,13 @@ static struct {
{ PCI_DEVICE_ID_INTEL_WHL_ID_Wx2, "Whiskeylake W (2+2)" },
{ PCI_DEVICE_ID_INTEL_CFL_ID_H, "Coffeelake-H" },
{ PCI_DEVICE_ID_INTEL_CFL_ID_S, "Coffeelake-S" },
{ PCI_DEVICE_ID_INTEL_CML_ULT, "CometLake-U (4+2)" },
{ PCI_DEVICE_ID_INTEL_CML_ULT_6_2, "CometLake-U (6+2)" },
{ PCI_DEVICE_ID_INTEL_CML_ULX, "CometLake-ULX (4+2)" },
{ PCI_DEVICE_ID_INTEL_CML_S, "CometLake-S (6+2)" },
{ PCI_DEVICE_ID_INTEL_CML_S_10_2, "CometLake-S (10+2)" },
{ PCI_DEVICE_ID_INTEL_CML_H, "CometLake-H (6+2)" },
{ PCI_DEVICE_ID_INTEL_CML_H_8_2, "CometLake-H (8+2)" },
};
static struct {
@ -86,6 +93,24 @@ static struct {
{ PCI_DEVICE_ID_INTEL_WHL_GT2_ULT_1, "Whiskeylake ULT GT1" },
{ PCI_DEVICE_ID_INTEL_CFL_H_GT2, "Coffeelake-H GT2" },
{ PCI_DEVICE_ID_INTEL_CFL_S_GT2, "Coffeelake-S GT2" },
{ PCI_DEVICE_ID_INTEL_CML_GT1_ULT_1, "CometLake ULT GT1" },
{ PCI_DEVICE_ID_INTEL_CML_GT1_ULT_2, "CometLake ULT GT1" },
{ PCI_DEVICE_ID_INTEL_CML_GT2_ULT_1, "CometLake ULT GT2" },
{ PCI_DEVICE_ID_INTEL_CML_GT2_ULT_2, "CometLake ULT GT2" },
{ PCI_DEVICE_ID_INTEL_CML_GT1_ULT_3, "CometLake ULT GT1" },
{ PCI_DEVICE_ID_INTEL_CML_GT1_ULT_4, "CometLake ULT GT1" },
{ PCI_DEVICE_ID_INTEL_CML_GT2_ULT_3, "CometLake ULT GT2" },
{ PCI_DEVICE_ID_INTEL_CML_GT2_ULT_4, "CometLake ULT GT2" },
{ PCI_DEVICE_ID_INTEL_CML_GT1_ULX_1, "CometLake ULX GT1" },
{ PCI_DEVICE_ID_INTEL_CML_GT2_ULX_1, "CometLake ULX GT2" },
{ PCI_DEVICE_ID_INTEL_CML_GT1_S_1, "CometLake S GT1" },
{ PCI_DEVICE_ID_INTEL_CML_GT1_S_2, "CometLake S GT1" },
{ PCI_DEVICE_ID_INTEL_CML_GT2_S_1, "CometLake S GT2" },
{ PCI_DEVICE_ID_INTEL_CML_GT2_S_2, "CometLake S GT2" },
{ PCI_DEVICE_ID_INTEL_CML_GT1_H_1, "CometLake H GT1" },
{ PCI_DEVICE_ID_INTEL_CML_GT1_H_2, "CometLake H GT1" },
{ PCI_DEVICE_ID_INTEL_CML_GT2_H_1, "CometLake H GT2" },
{ PCI_DEVICE_ID_INTEL_CML_GT2_H_2, "CometLake H GT2" },
};
static uint8_t get_dev_revision(pci_devfn_t dev)

18
src/soc/intel/common/block/graphics/graphics.c
View File

@ -151,6 +151,24 @@ static const unsigned short pci_device_ids[] = {
PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_5,
PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_6,
PCI_DEVICE_ID_INTEL_ICL_GT3_ULT,
PCI_DEVICE_ID_INTEL_CML_GT1_ULT_1,
PCI_DEVICE_ID_INTEL_CML_GT1_ULT_2,
PCI_DEVICE_ID_INTEL_CML_GT2_ULT_1,
PCI_DEVICE_ID_INTEL_CML_GT2_ULT_2,
PCI_DEVICE_ID_INTEL_CML_GT1_ULT_3,
PCI_DEVICE_ID_INTEL_CML_GT1_ULT_4,
PCI_DEVICE_ID_INTEL_CML_GT2_ULT_3,
PCI_DEVICE_ID_INTEL_CML_GT2_ULT_4,
PCI_DEVICE_ID_INTEL_CML_GT1_ULX_1,
PCI_DEVICE_ID_INTEL_CML_GT2_ULX_1,
PCI_DEVICE_ID_INTEL_CML_GT1_S_1,
PCI_DEVICE_ID_INTEL_CML_GT1_S_2,
PCI_DEVICE_ID_INTEL_CML_GT2_S_1,
PCI_DEVICE_ID_INTEL_CML_GT2_S_2,
PCI_DEVICE_ID_INTEL_CML_GT1_H_1,
PCI_DEVICE_ID_INTEL_CML_GT1_H_2,
PCI_DEVICE_ID_INTEL_CML_GT2_H_1,
PCI_DEVICE_ID_INTEL_CML_GT2_H_2,
0,
};

7
src/soc/intel/common/block/systemagent/systemagent.c
View File

@ -322,6 +322,13 @@ static const unsigned short systemagent_ids[] = {
PCI_DEVICE_ID_INTEL_ICL_ID_U_2_2,
PCI_DEVICE_ID_INTEL_ICL_ID_Y,
PCI_DEVICE_ID_INTEL_ICL_ID_Y_2,
PCI_DEVICE_ID_INTEL_CML_ULT,
PCI_DEVICE_ID_INTEL_CML_ULT_6_2,
PCI_DEVICE_ID_INTEL_CML_ULX,
PCI_DEVICE_ID_INTEL_CML_S,
PCI_DEVICE_ID_INTEL_CML_S_10_2,
PCI_DEVICE_ID_INTEL_CML_H,
PCI_DEVICE_ID_INTEL_CML_H_8_2,
0
};