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jetway/nf81-t56n-lf: Switch away from AGESA_LEGACY 

Change-Id: I6ad0c4cf2f0398f0b1efac1282822acf0d4a3610
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Kyösti Mälkki 2017-03-04 07:48:32 +02:00
parent 949491979c
commit f61ffcf9a4
3 changed files with 11 additions and 103 deletions
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1
src/mainboard/jetway/nf81-t56n-lf/Kconfig
View File

@ -18,7 +18,6 @@ if BOARD_JETWAY_NF81_T56N_LF
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select AGESA_LEGACY
select CPU_AMD_AGESA_FAMILY14
select NORTHBRIDGE_AMD_AGESA_FAMILY14
select SOUTHBRIDGE_AMD_CIMX_SB800

14
src/mainboard/jetway/nf81-t56n-lf/OemCustomize.c
View File

@ -17,7 +17,7 @@
#include "PlatformGnbPcieComplex.h"
#include <string.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
#include <PlatformMemoryConfiguration.h>
@ -35,7 +35,7 @@
*
**/
static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
{
AGESA_STATUS Status;
void *BrazosPcieComplexListPtr;
@ -176,7 +176,6 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
InitEarly->GnbConfig.PsppPolicy = 0;
return AGESA_SUCCESS;
}
/**
@ -188,12 +187,13 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
* If PlatformSpecificTable is populated, AGESA will base its settings on the
* data from the table. Otherwise, it will use its default conservative settings.
*/
const PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
static const PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
PSO_END
};
const struct OEM_HOOK OemCustomize = {
.InitEarly = OemInitEarly,
};
void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
{
InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
}

99
src/mainboard/jetway/nf81-t56n-lf/romstage.c
View File

@ -14,106 +14,15 @@
* GNU General Public License for more details.
*/
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <arch/acpi.h>
#include <arch/cpu.h>
#include <arch/io.h>
#include <arch/stages.h>
#include <cbmem.h>
#include <console/console.h>
#include <cpu/amd/agesa/s3_resume.h>
#include <cpu/x86/lapic.h>
#include <cpu/x86/bist.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <stdint.h>
#include <string.h>
#include <commonlib/loglevel.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/amd/mtrr.h>
#include <cpu/amd/car.h>
#include <sb_cimx.h>
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
#include <device/pnp_def.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <superio/fintek/common/fintek.h>
#include <superio/fintek/f71869ad/f71869ad.h>
/* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */
#define SERIAL_DEV PNP_DEV(0x2e, F71869AD_SP1)
/*
* Possible AGESA_STATUS values:
*
* 0x0 = AGESA_SUCCESS
* 0x1 = AGESA_UNSUPPORTED
* 0x2 = AGESA_BOUNDS_CHK
* 0x3 = AGESA_ALERT
* 0x4 = AGESA_WARNING
* 0x5 = AGESA_ERROR
* 0x6 = AGESA_CRITICAL
* 0x7 = AGESA_FATAL
*/
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
void board_BeforeAgesa(struct sysinfo *cb)
{
u32 val;
/* Must come first to enable PCI MMCONF. */
amd_initmmio();
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
sb_Poweron_Init();
post_code(0x31);
fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
}
/* Halt if there was a built in self test failure */
post_code(0x34);
report_bist_failure(bist);
/* Load MPB */
val = cpuid_eax(1);
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x37);
agesawrapper_amdinitreset();
post_code(0x39);
agesawrapper_amdinitearly();
int s3resume = acpi_is_wakeup_s3();
if (!s3resume) {
post_code(0x40);
agesawrapper_amdinitpost();
post_code(0x42);
agesawrapper_amdinitenv();
amd_initenv();
} else { /* S3 detect */
printk(BIOS_INFO, "S3 detected\n");
post_code(0x60);
agesawrapper_amdinitresume();
agesawrapper_amds3laterestore();
post_code(0x61);
prepare_for_resume();
}
post_code(0x50);
copy_and_run();
printk(BIOS_ERR, "Error: copy_and_run() returned!\n");
post_code(0x54); /* Should never see this post code. */
fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
}