jetway/nf81-t56n-lf: Switch away from AGESA_LEGACY
Change-Id: I6ad0c4cf2f0398f0b1efac1282822acf0d4a3610 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Kyösti Mälkki
parent
949491979c
commit
f61ffcf9a4
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@ -18,7 +18,6 @@ if BOARD_JETWAY_NF81_T56N_LF
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select AGESA_LEGACY
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select CPU_AMD_AGESA_FAMILY14
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select NORTHBRIDGE_AMD_AGESA_FAMILY14
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select SOUTHBRIDGE_AMD_CIMX_SB800
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@ -17,7 +17,7 @@
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#include "PlatformGnbPcieComplex.h"
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#include <string.h>
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#include <northbridge/amd/agesa/agesawrapper.h>
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#include <northbridge/amd/agesa/state_machine.h>
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#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
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#include <PlatformMemoryConfiguration.h>
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@ -35,7 +35,7 @@
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*
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**/
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static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
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void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
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{
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AGESA_STATUS Status;
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void *BrazosPcieComplexListPtr;
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@ -176,7 +176,6 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
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InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
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InitEarly->GnbConfig.PsppPolicy = 0;
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return AGESA_SUCCESS;
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}
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/**
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@ -188,12 +187,13 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
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* If PlatformSpecificTable is populated, AGESA will base its settings on the
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* data from the table. Otherwise, it will use its default conservative settings.
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*/
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const PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
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static const PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
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NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
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NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
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PSO_END
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};
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const struct OEM_HOOK OemCustomize = {
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.InitEarly = OemInitEarly,
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};
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void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
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{
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InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
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}
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@ -14,106 +14,15 @@
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* GNU General Public License for more details.
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*/
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#include <northbridge/amd/agesa/agesawrapper.h>
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#include <northbridge/amd/agesa/agesa_helper.h>
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#include <arch/acpi.h>
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#include <arch/cpu.h>
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#include <arch/io.h>
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#include <arch/stages.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include <cpu/amd/agesa/s3_resume.h>
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#include <cpu/x86/lapic.h>
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#include <cpu/x86/bist.h>
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#include <device/pci_def.h>
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#include <device/pci_ids.h>
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#include <stdint.h>
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#include <string.h>
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#include <commonlib/loglevel.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/cache.h>
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#include <cpu/amd/mtrr.h>
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#include <cpu/amd/car.h>
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#include <sb_cimx.h>
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#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
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#include <device/pnp_def.h>
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#include <northbridge/amd/agesa/state_machine.h>
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#include <superio/fintek/common/fintek.h>
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#include <superio/fintek/f71869ad/f71869ad.h>
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/* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */
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#define SERIAL_DEV PNP_DEV(0x2e, F71869AD_SP1)
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/*
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* Possible AGESA_STATUS values:
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*
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* 0x0 = AGESA_SUCCESS
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* 0x1 = AGESA_UNSUPPORTED
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* 0x2 = AGESA_BOUNDS_CHK
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* 0x3 = AGESA_ALERT
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* 0x4 = AGESA_WARNING
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* 0x5 = AGESA_ERROR
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* 0x6 = AGESA_CRITICAL
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* 0x7 = AGESA_FATAL
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*/
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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void board_BeforeAgesa(struct sysinfo *cb)
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{
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u32 val;
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/* Must come first to enable PCI MMCONF. */
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amd_initmmio();
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if (!cpu_init_detectedx && boot_cpu()) {
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post_code(0x30);
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sb_Poweron_Init();
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post_code(0x31);
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fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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console_init();
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}
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/* Halt if there was a built in self test failure */
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post_code(0x34);
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report_bist_failure(bist);
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/* Load MPB */
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val = cpuid_eax(1);
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printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
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printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
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post_code(0x37);
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agesawrapper_amdinitreset();
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post_code(0x39);
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agesawrapper_amdinitearly();
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int s3resume = acpi_is_wakeup_s3();
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if (!s3resume) {
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post_code(0x40);
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agesawrapper_amdinitpost();
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post_code(0x42);
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agesawrapper_amdinitenv();
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amd_initenv();
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} else { /* S3 detect */
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printk(BIOS_INFO, "S3 detected\n");
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post_code(0x60);
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agesawrapper_amdinitresume();
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agesawrapper_amds3laterestore();
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post_code(0x61);
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prepare_for_resume();
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}
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post_code(0x50);
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copy_and_run();
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printk(BIOS_ERR, "Error: copy_and_run() returned!\n");
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post_code(0x54); /* Should never see this post code. */
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fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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}
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