AGESA fam15: Drop code that was commented out
Only references to bus_rd890, bus_sp5100 and bus_sr5650 were in code sections that had been commented out. Change-Id: If5552c409ce948c494345f49dbaad790b398bff8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6331 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
Kyösti Mälkki
parent
99c636f858
commit
f62659f643
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@ -31,7 +31,6 @@
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* and acpi_tables busnum is default.
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*/
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u8 bus_sb700[2];
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u8 bus_rd890[14];
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/*
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* Here you only need to set value in pci1234 for HT-IO that could be installed or not
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@ -51,7 +50,6 @@ u32 hcdnx[] = {
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};
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u32 sbdn_sb700;
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u32 sbdn_rd890;
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void get_bus_conf(void)
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{
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@ -65,13 +63,9 @@ void get_bus_conf(void)
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for (i = 0; i < ARRAY_SIZE(bus_sb700); i++) {
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bus_sb700[i] = 0;
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}
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for (i = 0; i < ARRAY_SIZE(bus_rd890); i++) {
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bus_rd890[i] = 0;
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}
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bus_rd890[0] = (pci1234x[0] >> 16) & 0xff;
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bus_sb700[0] = bus_rd890[0];
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bus_sb700[0] = (pci1234x[0] >> 16) & 0xff;
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/* sb700 */
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dev = dev_find_slot(bus_sb700[0], PCI_DEVFN(sbdn_sb700 + 0x14, 4));
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@ -82,13 +76,5 @@ void get_bus_conf(void)
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bus_sb700[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
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}
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/* rd890 */
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for (i = 1; i < ARRAY_SIZE(bus_rd890); i++) {
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dev = dev_find_slot(bus_rd890[0], PCI_DEVFN(sbdn_rd890 + i, 0));
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if (dev) {
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bus_rd890[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
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}
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}
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printk(BIOS_DEBUG, "Mainboard - Get_bus_conf.c - get_bus_conf - End.\n");
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}
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@ -28,9 +28,7 @@
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#include <cpu/x86/lapic.h>
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#include <cpu/amd/amdfam15.h>
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extern u8 bus_rd890[14];
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extern u8 bus_sb700[2];
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extern u32 sbdn_rd890;
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extern u32 sbdn_sb700;
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@ -130,17 +128,6 @@ static void *smp_write_config_table(void *v)
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/* SATA */
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PCI_INT(0x0, 0x11, 0x0, 0x16); //6, INTG
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/* on board NIC & Slot PCIE. */
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/* configuration B doesnt need dev 5,6,7 */
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/*
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* PCI_INT(bus_rd890[0x5], 0x0, 0x0, 0x11);
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* PCI_INT(bus_rd890[0x6], 0x0, 0x0, 0x12);
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* PCI_INT(bus_rd890[0x7], 0x0, 0x0, 0x13);
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*/
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//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((13)<<2)|(0)), apicid_rd890, 28); /* dev d */
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//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_rd890[13], (((0)<<2)|(1)), apicid_rd890, 0); /* card behind dev13 */
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/* PCI slots */
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/* PCI_SLOT 0. */
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PCI_INT(bus_sb700[1], 0x5, 0x0, 0x14);
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@ -31,11 +31,6 @@
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* and acpi_tables busnum is default.
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*/
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u8 bus_sp5100[2];
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u8 bus_sr5650[14];
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u32 sbdn_sr5650;
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u32 sbdn_sp5100;
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void get_bus_conf(void)
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@ -48,13 +43,8 @@ void get_bus_conf(void)
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for (i = 0; i < ARRAY_SIZE(bus_sp5100); i++) {
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bus_sp5100[i] = 0;
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}
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for (i = 0; i < ARRAY_SIZE(bus_sr5650); i++) {
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bus_sr5650[i] = 0;
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}
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bus_sr5650[0] = 0;
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bus_sp5100[0] = bus_sr5650[0];
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bus_sp5100[0] = 0;
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/* sp5100 */
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dev = dev_find_slot(bus_sp5100[0], PCI_DEVFN(sbdn_sp5100 + 0x14, 4));
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@ -62,25 +52,4 @@ void get_bus_conf(void)
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if (dev) {
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bus_sp5100[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
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}
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/* sr5650 */
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for (i = 1; i < ARRAY_SIZE(bus_sr5650); i++) {
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dev = dev_find_slot(bus_sr5650[0], PCI_DEVFN(sbdn_sr5650 + i, 0));
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if (dev) {
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bus_sr5650[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
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}
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}
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/*
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for (i = 0; i < 4; i++) {
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dev = dev_find_slot(bus_sp5100[0], PCI_DEVFN(sbdn_sp5100 + 0x14, i));
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if (dev) {
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bus_sp5100[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
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}
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}
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*/
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/* I/O APICs: APIC ID Version State Address */
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}
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@ -28,9 +28,7 @@
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#include <cpu/x86/lapic.h>
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#include <cpu/amd/amdfam10_sysconf.h>
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extern u8 bus_sr5650[14];
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extern u8 bus_sp5100[2];
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extern u32 sbdn_sr5650;
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extern u32 sbdn_sp5100;
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static void *smp_write_config_table(void *v)
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@ -144,17 +142,6 @@ static void *smp_write_config_table(void *v)
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/* SATA */
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PCI_INT(0x0, 0x11, 0x0, 0x16); //6, INTG
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/* on board NIC & Slot PCIE. */
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/* configuration B doesnt need dev 5,6,7 */
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/*
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* PCI_INT(bus_sr5650[0x5], 0x0, 0x0, 0x11);
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* PCI_INT(bus_sr5650[0x6], 0x0, 0x0, 0x12);
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* PCI_INT(bus_sr5650[0x7], 0x0, 0x0, 0x13);
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*/
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//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((13)<<2)|(0)), apicid_sr5650, 28); /* dev d */
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//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[13], (((0)<<2)|(1)), apicid_sr5650, 0); /* card behind dev13 */
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/* PCI slots */
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/* PCI_SLOT 0. */
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PCI_INT(bus_sp5100[1], 0x5, 0x0, 0x14);
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@ -31,11 +31,6 @@
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* and acpi_tables busnum is default.
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*/
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u8 bus_sp5100[2];
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u8 bus_sr5650[14];
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u32 sbdn_sr5650;
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u32 sbdn_sp5100;
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void get_bus_conf(void)
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@ -48,13 +43,8 @@ void get_bus_conf(void)
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for (i = 0; i < 0; i++) {
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bus_sp5100[i] = 0;
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}
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for (i = 0; i < ARRAY_SIZE(bus_sr5650); i++) {
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bus_sr5650[i] = 0;
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}
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bus_sr5650[0] = 0;
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bus_sp5100[0] = bus_sr5650[0];
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bus_sp5100[0] = 0;
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/* sp5100 */
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dev = dev_find_slot(bus_sp5100[0], PCI_DEVFN(sbdn_sp5100 + 0x14, 4));
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@ -62,25 +52,4 @@ void get_bus_conf(void)
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if (dev) {
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bus_sp5100[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
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}
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/* sr5650 */
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for (i = 1; i < ARRAY_SIZE(bus_sr5650); i++) {
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dev = dev_find_slot(bus_sr5650[0], PCI_DEVFN(sbdn_sr5650 + i, 0));
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if (dev) {
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bus_sr5650[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
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}
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}
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/*
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for (i = 0; i < 4; i++) {
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dev = dev_find_slot(bus_sp5100[0], PCI_DEVFN(sbdn_sp5100 + 0x14, i));
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if (dev) {
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bus_sp5100[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
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}
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}
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*/
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/* I/O APICs: APIC ID Version State Address */
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}
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@ -28,9 +28,7 @@
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#include <cpu/x86/lapic.h>
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#include <cpu/amd/amdfam10_sysconf.h>
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extern u8 bus_sr5650[14];
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extern u8 bus_sp5100[2];
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extern u32 sbdn_sr5650;
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extern u32 sbdn_sp5100;
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static void *smp_write_config_table(void *v)
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@ -144,17 +142,6 @@ static void *smp_write_config_table(void *v)
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/* SATA */
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PCI_INT(0x0, 0x11, 0x0, 0x16); //6, INTG
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/* on board NIC & Slot PCIE. */
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/* configuration B doesnt need dev 5,6,7 */
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/*
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* PCI_INT(bus_sr5650[0x5], 0x0, 0x0, 0x11);
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* PCI_INT(bus_sr5650[0x6], 0x0, 0x0, 0x12);
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* PCI_INT(bus_sr5650[0x7], 0x0, 0x0, 0x13);
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*/
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//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((13)<<2)|(0)), apicid_sr5650, 28); /* dev d */
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//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[13], (((0)<<2)|(1)), apicid_sr5650, 0); /* card behind dev13 */
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/* PCI slots */
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/* PCI_SLOT 0. */
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PCI_INT(bus_sp5100[1], 0x5, 0x0, 0x14);
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@ -30,11 +30,6 @@
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* and acpi_tables busnum is default.
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*/
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u8 bus_sp5100[2];
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u8 bus_sr5650[14];
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u32 sbdn_sr5650;
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u32 sbdn_sp5100;
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void get_bus_conf(void);
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@ -49,13 +44,8 @@ void get_bus_conf(void)
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for (i = 0; i < 0; i++) {
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bus_sp5100[i] = 0;
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}
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for (i = 0; i < ARRAY_SIZE(bus_sr5650); i++) {
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bus_sr5650[i] = 0;
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}
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bus_sr5650[0] = 0;
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bus_sp5100[0] = bus_sr5650[0];
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bus_sp5100[0] = 0;
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/* sp5100 */
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dev = dev_find_slot(bus_sp5100[0], PCI_DEVFN(sbdn_sp5100 + 0x14, 4));
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@ -63,23 +53,4 @@ void get_bus_conf(void)
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if (dev) {
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bus_sp5100[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
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}
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/* sr5650 */
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for (i = 1; i < ARRAY_SIZE(bus_sr5650); i++) {
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dev = dev_find_slot(bus_sr5650[0], PCI_DEVFN(sbdn_sr5650 + i, 0));
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if (dev) {
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bus_sr5650[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
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}
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}
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/*
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for (i = 0; i < 4; i++) {
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dev = dev_find_slot(bus_sp5100[0], PCI_DEVFN(sbdn_sp5100 + 0x14, i));
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if (dev) {
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bus_sp5100[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
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}
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}
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*/
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}
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@ -28,7 +28,6 @@
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#include <cpu/x86/lapic.h>
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#include <cpu/amd/amdfam10_sysconf.h>
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extern u8 bus_sr5650[14];
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extern u8 bus_sp5100[2];
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extern u32 sbdn_sr5650;
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extern u32 sbdn_sp5100;
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@ -144,17 +143,6 @@ static void *smp_write_config_table(void *v)
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/* SATA */
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PCI_INT(0x0, 0x11, 0x0, 0x16); //6, INTG
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/* on board NIC & Slot PCIE. */
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/* configuration B doesnt need dev 5,6,7 */
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/*
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* PCI_INT(bus_sr5650[0x5], 0x0, 0x0, 0x11);
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* PCI_INT(bus_sr5650[0x6], 0x0, 0x0, 0x12);
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* PCI_INT(bus_sr5650[0x7], 0x0, 0x0, 0x13);
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*/
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//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((13)<<2)|(0)), apicid_sr5650, 28); /* dev d */
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//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[13], (((0)<<2)|(1)), apicid_sr5650, 0); /* card behind dev13 */
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/* PCI slots */
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/* PCI_SLOT 0. */
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PCI_INT(bus_sp5100[1], 0x5, 0x0, 0x14);
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