From f6280bc6501a0ea8f1226f9177d80d614f75853e Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 5 Mar 2014 21:53:02 -0800 Subject: [PATCH] tegra124: Fix some bugs in the clock configuration macros. There were some missing parenthesis and some extra semicolons which this change adds and removes, respectively. BUG=chrome-os-partner:25467 TEST=Built and booted on nyan rev1. Verified that the same frequency calculated differently results in the same settings. Before operator precedence would pull apart the frequency calculation and use the pieces in the wrong order. BRANCH=None Original-Change-Id: I843d4ae9f7a2ae362926d94b6b77ef31d350a329 Original-Signed-off-by: Gabe Black Original-Reviewed-on: https://chromium-review.googlesource.com/189013 Original-Reviewed-by: Hung-Te Lin Original-Reviewed-by: Tom Warren Original-Reviewed-by: Julius Werner Original-Commit-Queue: Gabe Black Original-Tested-by: Gabe Black (cherry picked from commit 462e61ad898a4d6a99c1d161d77bde245c5b1f5c) Signed-off-by: Marc Jones Change-Id: Ifce3aac262cf5e2ec0496c5b3ad894bf6f0f9a46 Reviewed-on: http://review.coreboot.org/7416 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks --- src/soc/nvidia/tegra124/include/soc/clock.h | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/soc/nvidia/tegra124/include/soc/clock.h b/src/soc/nvidia/tegra124/include/soc/clock.h index 9f3f0a48d9..c0a3f398e3 100644 --- a/src/soc/nvidia/tegra124/include/soc/clock.h +++ b/src/soc/nvidia/tegra124/include/soc/clock.h @@ -1,4 +1,5 @@ /* + * Copyright 2014 Google Inc. * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it @@ -192,7 +193,7 @@ enum { * and voila, upper 7 bits are (ref/freq-1), and lowest bit is h. Since you * will assign this to a u8, it gets nicely truncated for you. */ -#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2) +#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / (FREQ)) - 2) /* Calculate clock frequency value from reference and clock divider value * The discussion in the book is pretty lacking. @@ -211,18 +212,18 @@ enum { * Since you multiply denominator * 2 (by NOT shifting it), * you multiply numerator * 2 to cancel it out. */ -#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2)) +#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / ((REG) + 2)) #define clock_configure_irregular_source(device, src, freq, src_id) \ clrsetbits_le32(&clk_rst->clk_src_##device, \ CLK_SOURCE_MASK | CLK_DIVISOR_MASK, \ src_id << CLK_SOURCE_SHIFT | \ - CLK_DIVIDER(TEGRA_##src##_KHZ, freq)); + CLK_DIVIDER(TEGRA_##src##_KHZ, freq)) /* Warning: Some devices just use different bits for the same sources for no * apparent reason. *Always* double-check the TRM before trusting this macro. */ #define clock_configure_source(device, src, freq) \ - clock_configure_irregular_source(device, src, freq, src); + clock_configure_irregular_source(device, src, freq, src) enum clock_source { /* Careful: Not true for all sources, always check TRM! */ PLLP = 0,