sb/intel/common: Refactor _PRT generation to support GSI-based tables
Newer Intel SoCs also support _PRT tables, but they route PCI devices to more than just PIRQs, and statically specify IRQs instead of using link devices. Extend/refactor intel_acpi_gen_def_acpi_pirq to support this additional use case. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ica420a3d12fd1d64c8fe6e4b326fd779b3f10868 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Tim Wawrzynczak
Nico Huber
parent
d26cdb3ea3
commit
f62c49474f
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@ -21,6 +21,7 @@
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#include <southbridge/intel/common/pciehp.h>
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#include <southbridge/intel/common/acpi_pirq_gen.h>
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#include <southbridge/intel/common/pmutil.h>
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#include <southbridge/intel/common/rcba_pirq.h>
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#include <southbridge/intel/common/rtc.h>
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#include <southbridge/intel/common/spi.h>
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#include <types.h>
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@ -2,101 +2,78 @@
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#include <acpi/acpigen.h>
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#include <acpi/acpigen_pci.h>
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#include <console/console.h>
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#include <device/pci_def.h>
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#include <device/pci_ops.h>
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#include <string.h>
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#include "acpi_pirq_gen.h"
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enum emit_type {
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EMIT_APIC,
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EMIT_PICM,
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};
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static int create_pirq_matrix(char matrix[32][4])
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static void gen_apic_route(const struct slot_pin_irq_map *pin_irq_map,
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unsigned int map_count)
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{
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struct device *dev;
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int num_devs = 0;
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for (unsigned int i = 0; i < map_count; i++)
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/*
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* The reason for subtracting PCI_INT_A from the pin given is
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* that PCI defines pins as 1-4, and _PRT uses 0-3.
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*/
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acpigen_write_PRT_GSI_entry(pin_irq_map[i].slot,
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pin_irq_map[i].pin - PCI_INT_A,
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pin_irq_map[i].apic_gsi);
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}
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for (dev = pcidev_on_root(0, 0); dev; dev = dev->sibling) {
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u8 pci_dev;
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u8 int_pin;
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pci_dev = PCI_SLOT(dev->path.pci.devfn);
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int_pin = pci_read_config8(dev, PCI_INTERRUPT_PIN);
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if (int_pin == PCI_INT_NONE || int_pin > PCI_INT_D ||
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matrix[pci_dev][int_pin - PCI_INT_A]
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!= PIRQ_NONE)
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static void gen_pic_route(const struct slot_pin_irq_map *pin_irq_map,
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unsigned int map_count,
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const struct pic_pirq_map *pirq_map)
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{
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for (unsigned int i = 0; i < map_count; i++) {
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enum pirq pirq = pin_irq_map[i].pic_pirq;
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unsigned int pin = pin_irq_map[i].pin - PCI_INT_A;
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if (pirq == PIRQ_INVALID)
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continue;
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matrix[pci_dev][int_pin - PCI_INT_A] =
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intel_common_map_pirq(dev, int_pin);
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printk(BIOS_SPEW, "ACPI_PIRQ_GEN: %s: pin=%d pirq=%d\n",
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dev_path(dev), int_pin - PCI_INT_A,
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matrix[pci_dev][int_pin - PCI_INT_A] - PIRQ_A);
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num_devs++;
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}
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return num_devs;
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}
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static void gen_pirq_route(const enum emit_type emit, const char *lpcb_path,
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char pci_int_mapping[32][4])
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{
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int pci_dev, int_pin;
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char buffer[DEVICE_PATH_MAX];
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char pirq;
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for (pci_dev = 0; pci_dev < 32; pci_dev++) {
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for (int_pin = 0; int_pin < 4; int_pin++) {
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pirq = pci_int_mapping[pci_dev][int_pin];
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if (pirq == PIRQ_NONE)
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continue;
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if (emit == EMIT_APIC) {
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const unsigned int gsi = 16 + pirq - PIRQ_A;
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acpigen_write_PRT_GSI_entry(pci_dev, int_pin, gsi);
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} else {
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snprintf(buffer, sizeof(buffer),
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"%s.LNK%c",
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lpcb_path, 'A' + pirq - PIRQ_A);
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acpigen_write_PRT_source_entry(pci_dev, int_pin, buffer, 0);
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}
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}
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if (pirq_map->type == PIRQ_GSI)
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acpigen_write_PRT_GSI_entry(pin_irq_map[i].slot,
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pin,
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pirq_map->gsi[pirq]);
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else
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acpigen_write_PRT_source_entry(pin_irq_map[i].slot,
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pin,
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pirq_map->source_path[pirq],
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0);
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}
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}
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void intel_acpi_gen_def_acpi_pirq(const struct device *dev)
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void intel_write_pci0_PRT(const struct slot_pin_irq_map *pin_irq_map,
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unsigned int map_count,
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const struct pic_pirq_map *pirq_map)
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{
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const char *lpcb_path = acpi_device_path(dev);
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char pci_int_mapping[32][4];
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int num_devs;
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printk(BIOS_DEBUG, "Generating ACPI PIRQ entries\n");
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if (!lpcb_path) {
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printk(BIOS_ERR, "ACPI_PIRQ_GEN: Missing LPCB ACPI path\n");
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return;
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}
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memset(pci_int_mapping, 0, sizeof(pci_int_mapping));
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num_devs = create_pirq_matrix(pci_int_mapping);
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/* \_SB.PCI0._PRT */
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acpigen_write_scope("\\_SB.PCI0");
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acpigen_write_method("_PRT", 0);
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acpigen_write_if();
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acpigen_emit_namestring("PICM");
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acpigen_emit_byte(RETURN_OP);
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acpigen_write_package(num_devs);
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gen_pirq_route(EMIT_APIC, lpcb_path, pci_int_mapping);
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acpigen_write_package(map_count);
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gen_apic_route(pin_irq_map, map_count);
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acpigen_pop_len(); /* package */
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acpigen_write_else();
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acpigen_emit_byte(RETURN_OP);
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acpigen_write_package(num_devs);
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gen_pirq_route(EMIT_PICM, lpcb_path, pci_int_mapping);
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acpigen_write_package(map_count);
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gen_pic_route(pin_irq_map, map_count, pirq_map);
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acpigen_pop_len(); /* package */
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acpigen_pop_len(); /* else PICM */
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acpigen_pop_len(); /* _PRT */
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acpigen_pop_len(); /* \_SB */
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}
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bool is_slot_pin_assigned(const struct slot_pin_irq_map *pin_irq_map,
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unsigned int map_count, unsigned int slot,
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enum pci_pin pin)
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{
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for (size_t i = 0; i < map_count; i++) {
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if (pin_irq_map[i].slot == slot && pin_irq_map[i].pin == pin)
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return true;
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}
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return false;
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}
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@ -3,16 +3,20 @@
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#ifndef INTEL_COMMON_ACPI_PIRQ_GEN_H
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#define INTEL_COMMON_ACPI_PIRQ_GEN_H
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#include <device/device.h>
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#define MAX_SLOTS 32
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enum pci_pin {
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PCI_INT_NONE = 0,
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PCI_INT_A,
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PCI_INT_B,
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PCI_INT_C,
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PCI_INT_D,
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PCI_INT_MAX = PCI_INT_D,
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};
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enum pirq {
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PIRQ_NONE = 0,
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PIRQ_A,
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PIRQ_B,
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PIRQ_C,
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@ -21,10 +25,63 @@ enum pirq {
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PIRQ_F,
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PIRQ_G,
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PIRQ_H,
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PIRQ_COUNT,
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PIRQ_INVALID = 0xff,
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};
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void intel_acpi_gen_def_acpi_pirq(const struct device *dev);
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enum pirq intel_common_map_pirq(const struct device *dev,
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const enum pci_pin pci_pin);
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/*
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* This struct represents an assignment of slot/pin -> IRQ. Some chipsets may
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* want to provide both PIC-mode and APIC-mode IRQs (e.g. selected using PICM
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* set by the OS), therefore a field for each of a PIRQ for PIC-mode and a
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* GSI for APIC-mode are provided.
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*
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* For APIC mode, only GSIs are supported (`acpi_gsi`).
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*
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* For PIC mode, if the pirq_map_type is PIRQ_GSI, then `pic_pirq` is used as an
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* index into `struct pic_pirq_map.gsi`, or for SOURCE_PATH, `pic_pirq` indexes
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* into `struct pic_pirq_map.source_path` to pick the path to the LNKx device.
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*
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* The reasoning for this structure is related to older vs. newer Intel
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* platforms; older platforms supported routing of PCI IRQs to a PIRQ
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* only. Newer platforms support routing IRQs to either a PIRQ or (for some PCI
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* devices) a non-PIRQ GSI.
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*/
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struct slot_pin_irq_map {
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unsigned int slot;
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enum pci_pin pin;
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/* PIRQ # for PIC mode */
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unsigned int pic_pirq;
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/* GSI # for APIC mode */
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unsigned int apic_gsi;
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};
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enum pirq_map_type {
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PIRQ_GSI,
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PIRQ_SOURCE_PATH,
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};
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/*
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* A PIRQ can be either be statically assigned a GSI or OSPM can use the Methods
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* on the ACPI device (source_path) to assign IRQs at runtime.
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*/
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struct pic_pirq_map {
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enum pirq_map_type type;
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union {
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unsigned int gsi[PIRQ_COUNT];
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char source_path[PIRQ_COUNT][DEVICE_PATH_MAX];
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};
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};
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/*
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* Generate an ACPI _PRT table by providing PIRQ and/or GSI information for each
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* slot/pin combination, and optionally providing paths to LNKx devices that can
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* provide IRQs in PIC mode.
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*/
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void intel_write_pci0_PRT(const struct slot_pin_irq_map *pin_irq_map,
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unsigned int map_count,
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const struct pic_pirq_map *pirq_map);
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bool is_slot_pin_assigned(const struct slot_pin_irq_map *pin_irq_map,
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unsigned int map_count, unsigned int slot, unsigned int pin);
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#endif
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@ -1,8 +1,10 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi_device.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <stdlib.h>
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#include <southbridge/intel/common/acpi_pirq_gen.h>
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#include <southbridge/intel/common/rcba_pirq.h>
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#include <southbridge/intel/common/rcba.h>
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@ -15,7 +17,7 @@ static const u32 pirq_dir_route_reg[MAX_SLOT - MIN_SLOT + 1] = {
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D26IR, D27IR, D28IR, D29IR, D30IR, D31IR,
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};
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enum pirq intel_common_map_pirq(const struct device *dev, const enum pci_pin pci_pin)
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static enum pirq map_pirq(const struct device *dev, const enum pci_pin pci_pin)
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{
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u8 slot = PCI_SLOT(dev->path.pci.devfn);
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u8 shift = 4 * (pci_pin - PCI_INT_A);
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@ -25,18 +27,66 @@ enum pirq intel_common_map_pirq(const struct device *dev, const enum pci_pin pci
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if (pci_pin < PCI_INT_A || pci_pin > PCI_INT_D) {
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printk(BIOS_ERR, "ACPI_PIRQ_GEN: Slot %d PCI pin %d out of bounds\n",
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slot, pci_pin);
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return PIRQ_NONE;
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return PIRQ_INVALID;
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}
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/* Slot 24 should not exist and has no D24IR but better be safe here */
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if (slot < MIN_SLOT || slot > MAX_SLOT || slot == 24) {
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/* non-PCH devices use 1:1 mapping. */
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return (enum pirq)pci_pin;
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return (enum pirq)(pci_pin - PCI_INT_A);
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}
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reg = pirq_dir_route_reg[slot - MIN_SLOT];
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pirq = (RCBA16(reg) >> shift) & 0x7;
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return (enum pirq)(PIRQ_A + pirq);
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return (enum pirq)pirq;
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}
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void intel_acpi_gen_def_acpi_pirq(const struct device *lpc)
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{
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struct slot_pin_irq_map *pin_irq_map;
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const char *lpcb_path = acpi_device_path(lpc);
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struct pic_pirq_map pirq_map = {0};
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unsigned int map_count = 0;
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int i;
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if (!lpcb_path) {
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printk(BIOS_ERR, "ACPI_PIRQ_GEN: Missing LPCB ACPI path\n");
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return;
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}
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printk(BIOS_DEBUG, "Generating ACPI PIRQ entries\n");
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pin_irq_map = calloc(sizeof(struct slot_pin_irq_map), MAX_SLOTS * PCI_INT_MAX);
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pirq_map.type = PIRQ_SOURCE_PATH;
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for (i = 0; i < PIRQ_COUNT; i++)
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snprintf(pirq_map.source_path[i], sizeof(pirq_map.source_path[i]),
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"%s.LNK%c", lpcb_path, 'A' + i);
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for (struct device *dev = pcidev_on_root(0, 0); dev; dev = dev->sibling) {
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const u8 pci_dev = PCI_SLOT(dev->path.pci.devfn);
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const u8 int_pin = pci_read_config8(dev, PCI_INTERRUPT_PIN);
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if (int_pin < PCI_INT_A || int_pin > PCI_INT_D)
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continue;
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if (is_slot_pin_assigned(pin_irq_map, map_count, pci_dev, int_pin))
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continue;
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enum pirq pirq = map_pirq(dev, int_pin);
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pin_irq_map[map_count].slot = pci_dev;
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pin_irq_map[map_count].pin = (enum pci_pin)int_pin;
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pin_irq_map[map_count].pic_pirq = pirq;
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/* PIRQs are mapped to GSIs starting at 16 */
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pin_irq_map[map_count].apic_gsi = 16 + (unsigned int)pirq;
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printk(BIOS_SPEW, "ACPI_PIRQ_GEN: %s: pin=%d pirq=%d\n",
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dev_path(dev), int_pin - PCI_INT_A,
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pin_irq_map[map_count].pic_pirq);
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map_count++;
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}
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intel_write_pci0_PRT(pin_irq_map, map_count, &pirq_map);
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free(pin_irq_map);
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}
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@ -3,6 +3,8 @@
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#ifndef SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ_H
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#define SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ_H
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#include <device/device.h>
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/*
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* The DnnIR registers use common RCBA offsets across these chipsets:
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* bd82x6x, i82801, i89xx, ibexpeak, lynxpoint
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@ -23,4 +25,7 @@
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#define D20IR 0x3160 /* 16bit */
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#define D19IR 0x3168 /* 16bit */
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/* Generate an ACPI _PRT table for chipsets that use PIRQs exclusively */
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void intel_acpi_gen_def_acpi_pirq(const struct device *dev);
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#endif /* SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ_H */
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@ -16,6 +16,7 @@
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#include <acpi/acpigen.h>
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#include <arch/smp/mpspec.h>
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#include <southbridge/intel/common/acpi_pirq_gen.h>
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#include <southbridge/intel/common/rcba_pirq.h>
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#include <southbridge/intel/common/hpet.h>
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#include <southbridge/intel/common/pmbase.h>
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#include <southbridge/intel/common/spi.h>
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@ -19,6 +19,7 @@
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#include <southbridge/intel/common/pciehp.h>
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#include <southbridge/intel/common/pmutil.h>
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#include <southbridge/intel/common/acpi_pirq_gen.h>
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#include <southbridge/intel/common/rcba_pirq.h>
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#define NMI_OFF 0
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@ -20,6 +20,7 @@
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#include <southbridge/intel/common/pciehp.h>
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#include <southbridge/intel/common/pmutil.h>
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#include <southbridge/intel/common/acpi_pirq_gen.h>
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#include <southbridge/intel/common/rcba_pirq.h>
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#define NMI_OFF 0
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@ -21,6 +21,7 @@
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#include <southbridge/intel/common/pciehp.h>
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#include <southbridge/intel/common/acpi_pirq_gen.h>
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#include <southbridge/intel/common/spi.h>
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#include <southbridge/intel/common/rcba_pirq.h>
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#define NMI_OFF 0
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@ -17,6 +17,7 @@
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#include "pch.h"
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#include <acpi/acpigen.h>
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#include <southbridge/intel/common/acpi_pirq_gen.h>
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#include <southbridge/intel/common/rcba_pirq.h>
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#include <southbridge/intel/common/rtc.h>
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#include <southbridge/intel/common/spi.h>
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#include <types.h>
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Reference in New Issue