soc/intel/cannonlake: Fix GPIO reporting
The kernel GPIO driver only expects some GPIO communities to be exported in the _CRS and it will not work correctly if the other communities are exported. CNL-LP: GPIO communities 0, 1, 4 CNL-H: GPIO communities 0, 1, 3, 4 Additionally one of the pin offset values was incorrect in GPIO community 1 for CNL-LP. This doesn't have any specific failure mode but it was found when auditing the GPIO code. Details of the kernel expected map can be found in the linux kernel at drivers/pinctrl/intel/pinctrl-cannonlake.c BUG=b:120686247 TEST=check /sys/kernel/debug/pinctrl/INT34BB:00/pins to ensure that pins >= 198 are not reading all zeros for the pin config registers. Change-Id: Ie1a2f3b9f9f4b24a9fc57e468dee50e99753912f Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/30112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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@ -28,13 +28,16 @@ Device (GPIO)
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{
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Memory32Fixed (ReadWrite, 0, 0, COM0)
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Memory32Fixed (ReadWrite, 0, 0, COM1)
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Memory32Fixed (ReadWrite, 0, 0, COM2)
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Memory32Fixed (ReadWrite, 0, 0, COM3)
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Memory32Fixed (ReadWrite, 0, 0, COM4)
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Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
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{ GPIO_IRQ14 }
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})
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/*
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* GPIO communities 0, 1, and 4 are exported for the OS.
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* This is based on the Linux kernel provided community map at
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* drivers/pinctrl/intel/pinctrl-cannonlake.c:cnllp_communities[]
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*/
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Method (_CRS, 0, NotSerialized)
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{
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/* GPIO Community 0 */
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@ -49,19 +52,6 @@ Device (GPIO)
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Store (^^PCRB (PID_GPIOCOM1), BAS1)
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Store (GPIO_BASE_SIZE, LEN1)
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/* GPIO Community 2 */
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CreateDWordField (^RBUF, ^COM2._BAS, BAS2)
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CreateDWordField (^RBUF, ^COM2._LEN, LEN2)
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Store (^^PCRB (PID_GPIOCOM2), BAS2)
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Store (GPIO_BASE_SIZE, LEN2)
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/* GPIO Community 3 */
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CreateDWordField (^RBUF, ^COM3._BAS, BAS3)
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CreateDWordField (^RBUF, ^COM3._LEN, LEN3)
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Store (^^PCRB (PID_GPIOCOM3), BAS3)
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Store (GPIO_BASE_SIZE, LEN3)
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/* GPIO Community 4 */
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CreateDWordField (^RBUF, ^COM4._BAS, BAS4)
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CreateDWordField (^RBUF, ^COM4._LEN, LEN4)
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@ -27,13 +27,17 @@ Device (GPIO)
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{
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Memory32Fixed (ReadWrite, 0, 0, COM0)
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Memory32Fixed (ReadWrite, 0, 0, COM1)
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Memory32Fixed (ReadWrite, 0, 0, COM2)
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Memory32Fixed (ReadWrite, 0, 0, COM3)
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Memory32Fixed (ReadWrite, 0, 0, COM4)
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Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
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{ GPIO_IRQ14 }
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})
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/*
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* GPIO communities 0, 1, 3, and 4 are exported for the OS.
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* This is based on the Linux kernel provided community map at
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* drivers/pinctrl/intel/pinctrl-cannonlake.c:cnhl_communities[]
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*/
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Method (_CRS, 0, NotSerialized)
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{
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/* GPIO Community 0 */
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@ -48,19 +52,12 @@ Device (GPIO)
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Store (^^PCRB (PID_GPIOCOM1), BAS1)
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Store (GPIO_BASE_SIZE, LEN1)
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/* GPIO Community 2 */
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CreateDWordField (^RBUF, ^COM2._BAS, BAS2)
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CreateDWordField (^RBUF, ^COM2._LEN, LEN2)
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Store (^^PCRB (PID_GPIOCOM2), BAS2)
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Store (GPIO_BASE_SIZE, LEN2)
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/* GPIO Community 3 */
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CreateDWordField (^RBUF, ^COM3._BAS, BAS3)
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CreateDWordField (^RBUF, ^COM3._LEN, LEN3)
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Store (^^PCRB (PID_GPIOCOM3), BAS3)
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Store (GPIO_BASE_SIZE, LEN3)
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/* GPIO Community 4 */
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CreateDWordField (^RBUF, ^COM4._BAS, BAS4)
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CreateDWordField (^RBUF, ^COM4._LEN, LEN4)
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@ -43,7 +43,7 @@ static const struct pad_group cnl_community1_groups[] = {
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INTEL_GPP(GPP_D0, GPP_D0, GPIO_RSVD_12), /* GPP_D */
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INTEL_GPP(GPP_D0, GPP_F0, GPP_F23), /* GPP_F */
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INTEL_GPP(GPP_D0, GPP_H0, GPP_H23), /* GPP_H */
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INTEL_GPP(GPP_D0, GPIO_RSVD_12, GPIO_RSVD_52), /* VGPIO */
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INTEL_GPP(GPP_D0, GPIO_RSVD_13, GPIO_RSVD_52), /* VGPIO */
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};
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static const struct pad_group cnl_community2_groups[] = {
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