northbridge/intel/x4x/dq_dqs.c: Remove repeated word
Change-Id: Iee24c6bf82ab6ff6691707ed0c388cfe492cc925 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49523 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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@ -746,7 +746,7 @@ static enum cb_err increment_to_dqs_edge(struct sysinfo *s, u8 channel, u8 rank)
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* DDR3 uses flyby topology where the clock signal takes a different path
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* than the data signal, to allow for better signal intergrity.
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* Therefore the delay on the data signals needs to account for this.
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* This is done by by sampleling the the DQS write (tx) signal back over
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* This is done by sampleling the DQS write (tx) signal back over
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* the DQ signal and looking for delay values where the sample transitions
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* from high to low.
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* Here the following is done:
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