soc/amd/picasso/fch: change sb prefix of sb_clk_output_48Mhz to fch

Picasso has an integrated FCH and no south bridge, so change the sb
prefix to fch.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I82aed68104ea9570827646c818e100bd7e04d1af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56526
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/amd/picasso/fch.c

@@ -86,7 +86,7 @@ const struct irq_idx_name *sb_get_apic_reg_association(size_t *size)
 	return irq_association;
 }
 
-static void sb_clk_output_48Mhz(void)
+static void fch_clk_output_48Mhz(void)
 {
 	u32 ctrl;
 	const struct soc_amd_picasso_config *cfg = config_of_soc();
@@ -231,7 +231,7 @@ void fch_init(void *chip_info)
 
 	gpp_clk_setup();
 
-	sb_clk_output_48Mhz();
+	fch_clk_output_48Mhz();
 
 	sb_rfmux_config_override();
 }