amd/amdmct/mct_ddr3: Partially fix up registered DIMMs on Fam10h
Sufficient support has been added to allow booting with registered DIMMs on the KGPE-D16 in certain slots. ECC support needs additional work; the ECC data lanes appear to cause boot failures in some slots. Change-Id: Ieaf4cbf351908e5a89760be49a6667dc55dbc575 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12017 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Timothy Pearson
Martin Roth
parent
474ff3dee5
commit
f682d0028c
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@ -311,6 +311,120 @@ static uint16_t mhz_to_memclk_config(uint16_t freq)
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return fam10h_mhz_to_memclk_config(freq) + 1;
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}
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static uint32_t fam10h_address_timing_compensation_code(struct DCTStatStruc *pDCTstat, uint8_t dct)
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{
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uint8_t MaxDimmsInstallable = mctGet_NVbits(NV_MAX_DIMMS_PER_CH);
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uint8_t package_type;
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uint32_t calibration_code = 0;
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package_type = mctGet_NVbits(NV_PACK_TYPE);
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uint16_t MemClkFreq = (Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x94) & 0x7) + 1;
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/* Obtain number of DIMMs on channel */
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uint8_t dimm_count = pDCTstat->MAdimms[dct];
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uint8_t rank_count_dimm0;
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uint8_t rank_count_dimm1;
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if (package_type == PT_GR) {
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/* Socket G34 */
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if (pDCTstat->Status & (1 << SB_Registered)) {
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/* RDIMM */
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/* Fam10h BKDG Rev. 3.62 section 2.8.9.5.8 Tables 60 - 61 */
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if (MaxDimmsInstallable == 1) {
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if (MemClkFreq == 0x4) {
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/* DDR3-800 */
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calibration_code = 0x00000000;
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} else if (MemClkFreq == 0x5) {
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/* DDR3-1066 */
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calibration_code = 0x003c3c3c;
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} else if (MemClkFreq == 0x6) {
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/* DDR3-1333 */
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calibration_code = 0x003a3a3a;
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}
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} else if (MaxDimmsInstallable == 2) {
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if (dimm_count == 1) {
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/* 1 DIMM detected */
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if (MemClkFreq == 0x4) {
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/* DDR3-800 */
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calibration_code = 0x00000000;
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} else if (MemClkFreq == 0x5) {
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/* DDR3-1066 */
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calibration_code = 0x003c3c3c;
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} else if (MemClkFreq == 0x6) {
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/* DDR3-1333 */
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calibration_code = 0x003a3a3a;
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}
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} else if (dimm_count == 2) {
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/* 2 DIMMs detected */
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if (MemClkFreq == 0x4) {
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/* DDR3-800 */
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calibration_code = 0x00000000;
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} else if (MemClkFreq == 0x5) {
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/* DDR3-1066 */
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calibration_code = 0x003a3c3a;
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} else if (MemClkFreq == 0x6) {
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/* DDR3-1333 */
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calibration_code = 0x00383a38;
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}
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}
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} else if (MaxDimmsInstallable == 3) {
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/* TODO
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* 3 DIMM/channel support unimplemented
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*/
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}
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} else {
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/* UDIMM */
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/* Fam10h BKDG Rev. 3.62 section 2.8.9.5.8 Table 56 */
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if (dimm_count == 1) {
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/* 1 DIMM detected */
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rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct];
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if (MemClkFreq == 0x4) {
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/* DDR3-800 */
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if (rank_count_dimm0 == 1)
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calibration_code = 0x00000000;
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else
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calibration_code = 0x003b0000;
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} else if (MemClkFreq == 0x5) {
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/* DDR3-1066 */
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if (rank_count_dimm0 == 1)
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calibration_code = 0x00000000;
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else
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calibration_code = 0x00380000;
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} else if (MemClkFreq == 0x6) {
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/* DDR3-1333 */
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if (rank_count_dimm0 == 1)
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calibration_code = 0x00000000;
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else
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calibration_code = 0x00360000;
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}
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} else if (dimm_count == 2) {
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/* 2 DIMMs detected */
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rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct];
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rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct];
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if (MemClkFreq == 0x4) {
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/* DDR3-800 */
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calibration_code = 0x00390039;
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} else if (MemClkFreq == 0x5) {
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/* DDR3-1066 */
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calibration_code = 0x00350037;
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} else if (MemClkFreq == 0x6) {
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/* DDR3-1333 */
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calibration_code = 0x00000035;
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}
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}
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}
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} else {
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/* TODO
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* Other socket support unimplemented
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*/
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}
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return calibration_code;
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}
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static uint32_t fam15h_phy_predriver_calibration_code(struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t drive_strength)
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{
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uint8_t lrdimm = 0;
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@ -1005,7 +1119,7 @@ static uint32_t fam15h_address_timing_compensation_code(struct DCTStatStruc *pDC
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/* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 74 */
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if (MaxDimmsInstallable == 1) {
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if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) {
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/* DDR3-667 - DDR3-800*/
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/* DDR3-667 - DDR3-800 */
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calibration_code = 0x00000000;
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} else if (MemClkFreq == 0xa) {
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/* DDR3-1066 */
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@ -1021,7 +1135,7 @@ static uint32_t fam15h_address_timing_compensation_code(struct DCTStatStruc *pDC
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if (dimm_count == 1) {
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/* 1 DIMM detected */
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if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) {
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/* DDR3-667 - DDR3-800*/
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/* DDR3-667 - DDR3-800 */
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calibration_code = 0x00000000;
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} else if (MemClkFreq == 0xa) {
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/* DDR3-1066 */
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@ -1036,7 +1150,7 @@ static uint32_t fam15h_address_timing_compensation_code(struct DCTStatStruc *pDC
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} else if (dimm_count == 2) {
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/* 2 DIMMs detected */
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if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) {
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/* DDR3-667 - DDR3-800*/
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/* DDR3-667 - DDR3-800 */
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calibration_code = 0x00000000;
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} else if (MemClkFreq == 0xa) {
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/* DDR3-1066 */
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@ -1314,6 +1428,26 @@ static void read_spd_bytes(struct MCTStatStruc *pMCTstat,
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}
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}
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#ifdef DEBUG_DIMM_SPD
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static void dump_spd_bytes(struct MCTStatStruc *pMCTstat,
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struct DCTStatStruc *pDCTstat, uint8_t dimm)
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{
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uint16_t byte;
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printk(BIOS_DEBUG, "SPD dump for DIMM %d\n ", dimm);
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for (byte = 0; byte < 16; byte++) {
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printk(BIOS_DEBUG, "%02x ", byte);
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}
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for (byte = 0; byte < 256; byte++) {
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if ((byte & 0xf) == 0x0) {
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printk(BIOS_DEBUG, "\n%02x ", byte >> 4);
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}
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printk(BIOS_DEBUG, "%02x ", pDCTstat->spd_data.spd_bytes[dimm][byte]);
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}
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printk(BIOS_DEBUG, "\n");
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}
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#endif
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#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
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static void calculate_and_store_spd_hashes(struct MCTStatStruc *pMCTstat,
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struct DCTStatStruc *pDCTstat)
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@ -1515,6 +1649,7 @@ restartinit:
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pMCTstat->GStatus |= 1 << GSB_ConfigRestored;
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#endif
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if (is_fam15h()) {
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printk(BIOS_DEBUG, "mctAutoInitMCT_D: mct_ForceNBPState0_Dis_Fam15\n");
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for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) {
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struct DCTStatStruc *pDCTstat;
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@ -1522,6 +1657,7 @@ restartinit:
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mct_ForceNBPState0_Dis_Fam15(pMCTstat, pDCTstat);
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}
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}
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} else {
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NodesWmem = 0;
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node_sys_base = 0;
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@ -1682,7 +1818,6 @@ restartinit:
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printk(BIOS_DEBUG, "mctAutoInitMCT_D: UMAMemTyping_D\n");
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UMAMemTyping_D(pMCTstat, pDCTstatA); /* Fix up for UMA sizing */
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}
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printk(BIOS_DEBUG, "mctAutoInitMCT_D: mct_ForceNBPState0_Dis_Fam15\n");
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for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) {
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@ -1691,6 +1826,7 @@ restartinit:
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mct_ForceNBPState0_Dis_Fam15(pMCTstat, pDCTstat);
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}
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}
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if (is_fam15h()) {
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enable_cc6 = 0;
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@ -2727,6 +2863,10 @@ static void DCTFinalInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *p
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dword = 1 << DisDramInterface;
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Set_NB32_DCT(pDCTstat->dev_dct, dct, 0x94, dword);
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dword = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x90);
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dword &= ~(1 << ParEn);
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Set_NB32_DCT(pDCTstat->dev_dct, dct, 0x90, dword);
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/* To maximize power savings when DisDramInterface=1b,
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* all of the MemClkDis bits should also be set.
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*/
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@ -3610,7 +3750,9 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
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dword++;
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}
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if (!(Status & (1 << SB_Registered)))
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if (Status & (1 << SB_Registered))
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DramConfigLo |= 1 << ParEn; /* Registered DIMMs */
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else
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DramConfigLo |= 1 << UnBuffDimm; /* Unbuffered DIMMs */
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if (mctGet_NVbits(NV_ECC_CAP))
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@ -4099,6 +4241,9 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
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if (status >= 0) { /* SPD access is ok */
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pDCTstat->DIMMPresent |= 1 << i;
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read_spd_bytes(pMCTstat, pDCTstat, i);
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#ifdef DEBUG_DIMM_SPD
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dump_spd_bytes(pMCTstat, pDCTstat, i);
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#endif
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crc_status = crcCheck(pDCTstat, i);
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if (!crc_status) {
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/* Try again in case there was a transient glitch */
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@ -4398,6 +4543,10 @@ static void mct_initDCT(struct MCTStatStruc *pMCTstat,
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val = 1 << DisDramInterface;
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Set_NB32_DCT(pDCTstat->dev_dct, 1, 0x94, val);
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val = Get_NB32_DCT(pDCTstat->dev_dct, 1, 0x90);
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val &= ~(1 << ParEn);
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Set_NB32_DCT(pDCTstat->dev_dct, 1, 0x90, val);
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/* To maximize power savings when DisDramInterface=1b,
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* all of the MemClkDis bits should also be set.
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*/
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@ -4552,6 +4701,7 @@ static u8 mct_PlatformSpec(struct MCTStatStruc *pMCTstat,
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index_reg = 0x98;
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Set_NB32_index_wait_DCT(dev, i, index_reg, 0x00, pDCTstat->CH_ODC_CTL[i]); /* Channel A/B Output Driver Compensation Control */
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Set_NB32_index_wait_DCT(dev, i, index_reg, 0x04, pDCTstat->CH_ADDR_TMG[i]); /* Channel A/B Output Driver Compensation Control */
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printk(BIOS_SPEW, "Programmed DCT %d timing/termination pattern %08x %08x\n", dct, pDCTstat->CH_ADDR_TMG[i], pDCTstat->CH_ODC_CTL[i]);
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}
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return pDCTstat->ErrCode;
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@ -4608,11 +4758,19 @@ static u8 mct_SPDCalcWidth(struct MCTStatStruc *pMCTstat,
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val = Get_NB32_DCT(pDCTstat->dev_dct, 0, 0x94);
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val |= 1 << DisDramInterface;
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Set_NB32_DCT(pDCTstat->dev_dct, 0, 0x94, val);
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val = Get_NB32_DCT(pDCTstat->dev_dct, 0, 0x90);
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val &= ~(1 << ParEn);
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Set_NB32_DCT(pDCTstat->dev_dct, 0, 0x90, val);
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}
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if (pDCTstat->DIMMValidDCT[1] == 0) {
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val = Get_NB32_DCT(pDCTstat->dev_dct, 1, 0x94);
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val |= 1 << DisDramInterface;
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Set_NB32_DCT(pDCTstat->dev_dct, 1, 0x94, val);
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val = Get_NB32_DCT(pDCTstat->dev_dct, 1, 0x90);
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val &= ~(1 << ParEn);
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Set_NB32_DCT(pDCTstat->dev_dct, 1, 0x90, val);
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}
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printk(BIOS_DEBUG, "SPDCalcWidth: Status %x\n", pDCTstat->Status);
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@ -6043,6 +6201,8 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat,
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dword &= ~(0xf); /* RdOdtTrnOnDly = read_odt_delay */
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dword |= (read_odt_delay & 0xf);
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Set_NB32_DCT(dev, dct, 0x240, dword);
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printk(BIOS_SPEW, "Programmed ODT pattern %08x %08x %08x %08x\n", odt_pattern_0, odt_pattern_1, odt_pattern_2, odt_pattern_3);
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} else if (pDCTstat->LogicalCPUID & AMD_DR_Dx) {
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if (pDCTstat->Speed == 3)
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dword = 0x00000800;
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@ -6178,6 +6338,8 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat,
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Set_NB32_index_wait_DCT(dev, i, 0xf0, 0x181, odt_pattern_0);
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Set_NB32_index_wait_DCT(dev, i, 0xf0, 0x182, odt_pattern_3);
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Set_NB32_index_wait_DCT(dev, i, 0xf0, 0x183, odt_pattern_2);
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printk(BIOS_SPEW, "Programmed ODT pattern %08x %08x %08x %08x\n", odt_pattern_0, odt_pattern_1, odt_pattern_2, odt_pattern_3);
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}
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}
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@ -17,7 +17,7 @@
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/* AM3/ASB2/C32/G34 DDR3 */
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static void Get_ChannelPS_Cfg0_D(u8 MAAdimms, u8 Speed, u8 MAAload,
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u32 *AddrTmgCTL, u32 *ODC_CTL,
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u32 *ODC_CTL,
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u8 *CMDmode);
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void mctGet_PS_Cfg_D(struct MCTStatStruc *pMCTstat,
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@ -30,9 +30,14 @@ void mctGet_PS_Cfg_D(struct MCTStatStruc *pMCTstat,
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} else {
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Get_ChannelPS_Cfg0_D(pDCTstat->MAdimms[dct], pDCTstat->Speed,
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pDCTstat->MAload[dct],
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&(pDCTstat->CH_ADDR_TMG[dct]), &(pDCTstat->CH_ODC_CTL[dct]),
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&(pDCTstat->CH_ODC_CTL[dct]),
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&pDCTstat->_2Tmode);
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if (pDCTstat->Status & (1 << SB_Registered)) {
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pDCTstat->_2Tmode = 1; /* Disable slow access mode */
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}
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pDCTstat->CH_ADDR_TMG[dct] = fam10h_address_timing_compensation_code(pDCTstat, dct);
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pDCTstat->CH_ODC_CTL[dct] |= 0x20000000; /* 60ohms */
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}
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@ -50,42 +55,25 @@ void mctGet_PS_Cfg_D(struct MCTStatStruc *pMCTstat,
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* : ODC_CTL - Output Driver Compensation Control Register Value
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* : CMDmode - CMD mode
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*/
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static void Get_ChannelPS_Cfg0_D( u8 MAAdimms, u8 Speed, u8 MAAload,
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u32 *AddrTmgCTL, u32 *ODC_CTL,
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static void Get_ChannelPS_Cfg0_D(u8 MAAdimms, u8 Speed, u8 MAAload,
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u32 *ODC_CTL,
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u8 *CMDmode)
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{
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*AddrTmgCTL = 0;
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*ODC_CTL = 0;
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*CMDmode = 1;
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if(MAAdimms == 1) {
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if(MAAload >= 16) {
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if(Speed == 4)
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*AddrTmgCTL = 0x003B0000;
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else if (Speed == 5)
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*AddrTmgCTL = 0x00380000;
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else if (Speed == 6)
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*AddrTmgCTL = 0x00360000;
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else
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*AddrTmgCTL = 0x00340000;
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} else {
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*AddrTmgCTL = 0x00000000;
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}
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if (MAAdimms == 1) {
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*ODC_CTL = 0x00113222;
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*CMDmode = 1;
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} else /* if(MAAdimms == 0) */ {
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if(Speed == 4) {
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*CMDmode = 1;
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*AddrTmgCTL = 0x00390039;
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} else if(Speed == 5) {
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*CMDmode = 1;
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*AddrTmgCTL = 0x00350037;
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} else if(Speed == 6) {
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*CMDmode = 2;
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*AddrTmgCTL = 0x00000035;
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} else {
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*CMDmode = 2;
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*AddrTmgCTL = 0x00000033;
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}
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*ODC_CTL = 0x00223323;
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}
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@ -237,13 +237,28 @@ static void CalcEccDQSPos_D(struct MCTStatStruc *pMCTstat,
|
|||
struct DCTStatStruc *pDCTstat,
|
||||
u16 like, u8 scale, u8 ChipSel)
|
||||
{
|
||||
u8 DQSDelay0, DQSDelay1;
|
||||
u16 DQSDelay;
|
||||
uint8_t DQSDelay0, DQSDelay1;
|
||||
int16_t delay_differential;
|
||||
uint16_t DQSDelay;
|
||||
|
||||
if (pDCTstat->Status & (1 << SB_Registered)) {
|
||||
return;
|
||||
}
|
||||
pDCTstat->ByteLane = 0x2;
|
||||
GetDQSDatStrucVal_D(pMCTstat, pDCTstat, ChipSel);
|
||||
DQSDelay0 = pDCTstat->DQSDelay;
|
||||
|
||||
pDCTstat->ByteLane = 0x3;
|
||||
GetDQSDatStrucVal_D(pMCTstat, pDCTstat, ChipSel);
|
||||
DQSDelay1 = pDCTstat->DQSDelay;
|
||||
|
||||
if (pDCTstat->Direction == DQS_READDIR) {
|
||||
DQSDelay = DQSDelay1;
|
||||
} else {
|
||||
delay_differential = (int16_t)DQSDelay1 - (int16_t)DQSDelay0;
|
||||
delay_differential += (int16_t)DQSDelay1;
|
||||
|
||||
DQSDelay = delay_differential;
|
||||
}
|
||||
} else {
|
||||
pDCTstat->ByteLane = like & 0xff;
|
||||
GetDQSDatStrucVal_D(pMCTstat, pDCTstat, ChipSel);
|
||||
DQSDelay0 = pDCTstat->DQSDelay;
|
||||
|
|
@ -269,6 +284,7 @@ static void CalcEccDQSPos_D(struct MCTStatStruc *pMCTstat,
|
|||
} else {
|
||||
DQSDelay += DQSDelay1;
|
||||
}
|
||||
}
|
||||
|
||||
pDCTstat->DQSDelay = (u8)DQSDelay;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -14,12 +14,39 @@
|
|||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
static uint16_t memclk_to_freq(uint16_t memclk) {
|
||||
uint16_t fam10h_freq_tab[] = {0, 0, 0, 400, 533, 667, 800};
|
||||
uint16_t fam15h_freq_tab[] = {0, 0, 0, 0, 333, 0, 400, 0, 0, 0, 533, 0, 0, 0, 667, 0, 0, 0, 800, 0, 0, 0, 933};
|
||||
|
||||
uint16_t mem_freq = 0;
|
||||
|
||||
if (is_fam15h()) {
|
||||
if (memclk < 0x17) {
|
||||
mem_freq = fam15h_freq_tab[memclk];
|
||||
}
|
||||
} else {
|
||||
if ((memclk > 0x0) && (memclk < 0x8)) {
|
||||
mem_freq = fam10h_freq_tab[memclk - 1];
|
||||
}
|
||||
}
|
||||
|
||||
return mem_freq;
|
||||
}
|
||||
|
||||
static uint32_t rc_word_value_to_ctl_bits(uint32_t value) {
|
||||
return ((value >> 2) & 3) << 16 | ((value & 3) << 3);
|
||||
}
|
||||
|
||||
static u32 mct_ControlRC(struct MCTStatStruc *pMCTstat,
|
||||
struct DCTStatStruc *pDCTstat, u32 MrsChipSel, u32 CtrlWordNum)
|
||||
{
|
||||
u8 Dimms, DimmNum, MaxDimm, Speed;
|
||||
u8 Dimms, DimmNum;
|
||||
u32 val;
|
||||
u32 dct = 0;
|
||||
uint8_t ddr_voltage_index;
|
||||
uint16_t mem_freq;
|
||||
uint8_t package_type = mctGet_NVbits(NV_PACK_TYPE);
|
||||
uint8_t MaxDimmsInstallable = mctGet_NVbits(NV_MAX_DIMMS_PER_CH);
|
||||
|
||||
DimmNum = (MrsChipSel >> 20) & 0xFE;
|
||||
|
||||
|
|
@ -28,54 +55,64 @@ static u32 mct_ControlRC(struct MCTStatStruc *pMCTstat,
|
|||
/* DimmNum ++; */
|
||||
/* cl +=8; */
|
||||
|
||||
MaxDimm = mctGet_NVbits(NV_MAX_DIMMS);
|
||||
Speed = pDCTstat->DIMMAutoSpeed;
|
||||
mem_freq = memclk_to_freq(pDCTstat->DIMMAutoSpeed);
|
||||
|
||||
if (pDCTstat->CSPresent_DCT[0] > 0) {
|
||||
dct = 0;
|
||||
} else if (pDCTstat->CSPresent_DCT[1] > 0 ){
|
||||
} else if (pDCTstat->CSPresent_DCT[1] > 0 ) {
|
||||
dct = 1;
|
||||
DimmNum ++;
|
||||
DimmNum++;
|
||||
}
|
||||
Dimms = pDCTstat->MAdimms[dct];
|
||||
|
||||
ddr_voltage_index = dct_ddr_voltage_index(pDCTstat, dct);
|
||||
|
||||
val = 0;
|
||||
if (CtrlWordNum == 0)
|
||||
val |= 1 << 1;
|
||||
val = 0x2;
|
||||
else if (CtrlWordNum == 1) {
|
||||
if (!((pDCTstat->DimmDRPresent | pDCTstat->DimmQRPresent) & (1 << DimmNum)))
|
||||
val |= 0xC; /* if single rank, set DBA1 and DBA0 */
|
||||
val = 0xC; /* if single rank, set DBA1 and DBA0 */
|
||||
} else if (CtrlWordNum == 2) {
|
||||
if (MaxDimm == 4) {
|
||||
if (Speed == 4) {
|
||||
if (((pDCTstat->DimmQRPresent & (1 << DimmNum)) && (Dimms == 1)) || (Dimms == 2))
|
||||
if (!(pDCTstat->MirrPresU_NumRegR & (1 << DimmNum)))
|
||||
val |= 1 << 2;
|
||||
} else {
|
||||
if (pDCTstat->MirrPresU_NumRegR & (1 << DimmNum))
|
||||
val |= 1 << 2;
|
||||
}
|
||||
} else {
|
||||
if (package_type == PT_GR) {
|
||||
/* Socket G34 */
|
||||
if (MaxDimmsInstallable == 2) {
|
||||
if (Dimms > 1)
|
||||
val |= 1 << 2;
|
||||
val = 0x4;
|
||||
}
|
||||
}
|
||||
} else if (CtrlWordNum == 3) {
|
||||
val |= (pDCTstat->CtrlWrd3 >> (DimmNum << 2)) & 0xFF;
|
||||
val = (pDCTstat->CtrlWrd3 >> (DimmNum << 2)) & 0xFF;
|
||||
} else if (CtrlWordNum == 4) {
|
||||
val |= (pDCTstat->CtrlWrd4 >> (DimmNum << 2)) & 0xFF;
|
||||
val = (pDCTstat->CtrlWrd4 >> (DimmNum << 2)) & 0xFF;
|
||||
} else if (CtrlWordNum == 5) {
|
||||
val |= (pDCTstat->CtrlWrd5 >> (DimmNum << 2)) & 0xFF;
|
||||
val = (pDCTstat->CtrlWrd5 >> (DimmNum << 2)) & 0xFF;
|
||||
} else if (CtrlWordNum == 8) {
|
||||
if (MaxDimm == 4)
|
||||
if (Speed == 4)
|
||||
if (pDCTstat->MirrPresU_NumRegR & (1 << DimmNum))
|
||||
val |= 1 << 2;
|
||||
} else if (CtrlWordNum == 9) {
|
||||
val |= 0xD; /* DBA1, DBA0, DA3 = 0 */
|
||||
if (package_type == PT_GR) {
|
||||
/* Socket G34 */
|
||||
if (MaxDimmsInstallable == 2) {
|
||||
val = 0x0;
|
||||
}
|
||||
val &= 0xffffff0f;
|
||||
}
|
||||
} else if (CtrlWordNum == 9) {
|
||||
val = 0xD; /* DBA1, DBA0, DA3 = 0 */
|
||||
} else if (CtrlWordNum == 10) {
|
||||
val = 0x0; /* Lowest operating frequency */
|
||||
} else if (CtrlWordNum == 11) {
|
||||
if (ddr_voltage_index & 0x4)
|
||||
val = 0x2; /* 1.25V */
|
||||
else if (ddr_voltage_index & 0x2)
|
||||
val = 0x1; /* 1.35V */
|
||||
else
|
||||
val = 0x0; /* 1.5V */
|
||||
} else if (CtrlWordNum >= 12) {
|
||||
val = 0x0; /* Unset */
|
||||
}
|
||||
val &= 0xf;
|
||||
|
||||
val = MrsChipSel | ((val >> 2) & 3) << 16 | ((val & 3) << 3);
|
||||
printk(BIOS_SPEW, "Preparing to send DIMM RC%d: %02x\n", CtrlWordNum, val);
|
||||
|
||||
val = MrsChipSel | rc_word_value_to_ctl_bits(val);
|
||||
|
||||
/* transfer Control word number to address [BA2,A2,A1,A0] */
|
||||
if (CtrlWordNum > 7) {
|
||||
|
|
@ -160,8 +197,10 @@ void FreqChgCtrlWrd(struct MCTStatStruc *pMCTstat,
|
|||
u32 MrsChipSel;
|
||||
u32 dev = pDCTstat->dev_dct;
|
||||
u32 val;
|
||||
uint16_t mem_freq;
|
||||
|
||||
pDCTstat->DIMMAutoSpeed = pDCTstat->TargetFreq;
|
||||
mem_freq = memclk_to_freq(pDCTstat->TargetFreq);
|
||||
for (MrsChipSel=0; MrsChipSel < 8; MrsChipSel++, MrsChipSel++) {
|
||||
if (pDCTstat->CSPresent & (1 << MrsChipSel)) {
|
||||
/* 2. Program F2x[1, 0]A8[CtrlWordCS]=bit mask for target chip selects. */
|
||||
|
|
@ -171,19 +210,31 @@ void FreqChgCtrlWrd(struct MCTStatStruc *pMCTstat,
|
|||
Set_NB32_DCT(dev, 0, 0xA8, val); /* TODO: dct 0 / 1 select */
|
||||
|
||||
/* Resend control word 10 */
|
||||
uint8_t freq_ctl_val = 0;
|
||||
mct_Wait(1600);
|
||||
switch (pDCTstat->TargetFreq) {
|
||||
case 5:
|
||||
mct_SendCtrlWrd(pMCTstat, pDCTstat, MrsChipSel << 20 | 0x4000A);
|
||||
switch (mem_freq) {
|
||||
case 333:
|
||||
case 400:
|
||||
freq_ctl_val = 0x0;
|
||||
break;
|
||||
case 6:
|
||||
mct_SendCtrlWrd(pMCTstat, pDCTstat, MrsChipSel << 20 | 0x40012);
|
||||
case 533:
|
||||
freq_ctl_val = 0x1;
|
||||
break;
|
||||
case 7:
|
||||
mct_SendCtrlWrd(pMCTstat, pDCTstat, MrsChipSel << 20 | 0x4001A);
|
||||
case 667:
|
||||
freq_ctl_val = 0x2;
|
||||
break;
|
||||
case 800:
|
||||
freq_ctl_val = 0x3;
|
||||
break;
|
||||
case 933:
|
||||
freq_ctl_val = 0x4;
|
||||
break;
|
||||
}
|
||||
|
||||
printk(BIOS_SPEW, "Preparing to send DIMM RC%d: %02x\n", 10, freq_ctl_val);
|
||||
|
||||
mct_SendCtrlWrd(pMCTstat, pDCTstat, MrsChipSel << 20 | 0x40002 | rc_word_value_to_ctl_bits(freq_ctl_val));
|
||||
|
||||
mct_Wait(1600);
|
||||
|
||||
/* Resend control word 2 */
|
||||
|
|
|
|||
|
|
@ -492,6 +492,8 @@ static u32 mct_MR2(struct MCTStatStruc *pMCTstat,
|
|||
ret |= ((dword >> 10) & 3) << 9;
|
||||
}
|
||||
|
||||
printk(BIOS_SPEW, "Going to send MR2 control word %08x\n", ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -521,6 +523,8 @@ static u32 mct_MR3(struct MCTStatStruc *pMCTstat,
|
|||
ret |= (dword >> 24) & 7;
|
||||
}
|
||||
|
||||
printk(BIOS_SPEW, "Going to send MR3 control word %08x\n", ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -615,6 +619,8 @@ static u32 mct_MR1(struct MCTStatStruc *pMCTstat,
|
|||
ret |= 1 << 12;
|
||||
}
|
||||
|
||||
printk(BIOS_SPEW, "Going to send MR1 control word %08x\n", ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -734,6 +740,8 @@ static u32 mct_MR0(struct MCTStatStruc *pMCTstat,
|
|||
ret |= 1 << 8;
|
||||
}
|
||||
|
||||
printk(BIOS_SPEW, "Going to send MR0 control word %08x\n", ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1740,6 +1740,7 @@ static void CalcEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat,
|
|||
u16 EccDQSLike;
|
||||
u8 EccDQSScale;
|
||||
u32 val, val0, val1;
|
||||
int16_t delay_differential;
|
||||
|
||||
EccDQSLike = pDCTstat->CH_EccDQSLike[Channel];
|
||||
EccDQSScale = pDCTstat->CH_EccDQSScale[Channel];
|
||||
|
|
@ -1749,6 +1750,15 @@ static void CalcEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat,
|
|||
u16 *p;
|
||||
p = pDCTstat->CH_D_B_RCVRDLY[Channel][ChipSel>>1];
|
||||
|
||||
if (pDCTstat->Status & (1 << SB_Registered)) {
|
||||
val0 = p[0x2];
|
||||
val1 = p[0x3];
|
||||
|
||||
delay_differential = (int16_t)val1 - (int16_t)val0;
|
||||
delay_differential += (int16_t)val1;
|
||||
|
||||
val = delay_differential;
|
||||
} else {
|
||||
/* DQS Delay Value of Data Bytelane
|
||||
* most like ECC byte lane */
|
||||
val0 = p[EccDQSLike & 0x07];
|
||||
|
|
@ -1756,7 +1766,6 @@ static void CalcEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat,
|
|||
* 2nd most like ECC byte lane */
|
||||
val1 = p[(EccDQSLike>>8) & 0x07];
|
||||
|
||||
if (!(pDCTstat->Status & (1 << SB_Registered))) {
|
||||
if(val0 > val1) {
|
||||
val = val0 - val1;
|
||||
} else {
|
||||
|
|
@ -1771,9 +1780,6 @@ static void CalcEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat,
|
|||
} else {
|
||||
val += val0;
|
||||
}
|
||||
} else {
|
||||
val = val1 - val0;
|
||||
val += val1;
|
||||
}
|
||||
|
||||
pDCTstat->CH_D_BC_RCVRDLY[Channel][ChipSel>>1] = val;
|
||||
|
|
|
|||
|
|
@ -926,7 +926,9 @@ void programODT(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, ui
|
|||
else if ((cs == 4) || (cs == 0))
|
||||
WrLvOdt1 = (dword & 0xf);
|
||||
} else {
|
||||
if (pDCTData->Status[DCT_STATUS_REGISTERED] == 0) {
|
||||
if (pDCTData->Status[DCT_STATUS_REGISTERED]) {
|
||||
WrLvOdt1 = WrLvOdtRegDimm(pMCTData, pDCTData, dimm);
|
||||
} else {
|
||||
if ((pDCTData->DctCSPresent & 0x05) == 0x05) {
|
||||
WrLvOdt1 = 0x03;
|
||||
} else if (bitTest((u32)pDCTData->DctCSPresent,(u8)(dimm*2+1))) {
|
||||
|
|
@ -934,14 +936,14 @@ void programODT(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, ui
|
|||
} else {
|
||||
WrLvOdt1 = (u8)bitTestSet(WrLvOdt1, dimm);
|
||||
}
|
||||
} else {
|
||||
WrLvOdt1 = WrLvOdtRegDimm(pMCTData, pDCTData, dimm);
|
||||
}
|
||||
}
|
||||
|
||||
set_DCT_ADDR_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT,
|
||||
DRAM_ADD_DCT_PHY_CONTROL_REG, 8, 11, (u32)WrLvOdt1);
|
||||
|
||||
printk(BIOS_SPEW, "Programmed DCT %d write levelling ODT pattern %08x\n", dct, WrLvOdt1);
|
||||
|
||||
}
|
||||
|
||||
#ifdef UNUSED_CODE
|
||||
|
|
@ -976,7 +978,7 @@ void procConfig(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, ui
|
|||
u16 Addl_Data_Offset, Addl_Data_Port;
|
||||
sMCTStruct *pMCTData = pDCTstat->C_MCTPtr;
|
||||
sDCTStruct *pDCTData = pDCTstat->C_DCTPtr[dct];
|
||||
u16 fam10h_freq_tab[] = {400, 533, 667, 800};
|
||||
uint16_t fam10h_freq_tab[] = {0, 0, 0, 400, 533, 667, 800};
|
||||
uint16_t fam15h_freq_tab[] = {0, 0, 0, 0, 333, 0, 400, 0, 0, 0, 533, 0, 0, 0, 667, 0, 0, 0, 800, 0, 0, 0, 933};
|
||||
|
||||
if (is_fam15h()) {
|
||||
|
|
@ -1089,21 +1091,18 @@ void procConfig(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, ui
|
|||
pDCTData->WLSeedPreGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_PreGross;
|
||||
}
|
||||
} else {
|
||||
if (pDCTData->Status[DCT_STATUS_REGISTERED])
|
||||
{
|
||||
if(pDCTData->RegMan1Present & ((1<<(dimm*2+dct))))
|
||||
{
|
||||
if (pDCTData->Status[DCT_STATUS_REGISTERED]) {
|
||||
uint8_t AddrCmdPrelaunch = 0; /* TODO: Fetch the correct value from RC2[0] */
|
||||
|
||||
/* The seed values below assume Pass 1 utilizes a 400MHz clock frequency (DDR3-800) */
|
||||
if (AddrCmdPrelaunch == 0) {
|
||||
Seed_Gross = 0x02;
|
||||
Seed_Fine = 0x16;
|
||||
}
|
||||
else
|
||||
{
|
||||
Seed_Fine = 0x01;
|
||||
} else {
|
||||
Seed_Gross = 0x02;
|
||||
Seed_Fine = 0x00;
|
||||
Seed_Fine = 0x11;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
} else {
|
||||
if (MemClkFreq == 6) {
|
||||
/* DDR-800 */
|
||||
Seed_Gross = 0x00;
|
||||
|
|
@ -1127,6 +1126,7 @@ void procConfig(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, ui
|
|||
*/
|
||||
pDCTData->WLGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_Gross;
|
||||
pDCTData->WLFineDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_Fine;
|
||||
printk(BIOS_SPEW, "\tLane %02x initial seed: %04x\n", ByteLane, ((Seed_Gross & 0x1f) << 5) | (Seed_Fine & 0x1f));
|
||||
}
|
||||
} else {
|
||||
/* Pass 2 */
|
||||
|
|
@ -1178,21 +1178,30 @@ void procConfig(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, ui
|
|||
|
||||
pDCTData->WLGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_PreGross;
|
||||
pDCTData->WLFineDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_Fine;
|
||||
|
||||
printk(BIOS_SPEW, "\tLane %02x new seed: %04x\n", ByteLane, ((Seed_Gross & 0x1f) << 5) | (Seed_Fine & 0x1f));
|
||||
}
|
||||
} else {
|
||||
u32 RegisterDelay, SeedTotal;
|
||||
uint32_t RegisterDelay;
|
||||
uint32_t SeedTotalPreScaling;
|
||||
uint32_t SeedTotal;
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||||
uint8_t AddrCmdPrelaunch = 0; /* TODO: Fetch the correct value from RC2[0] */
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for (ByteLane = 0; ByteLane < MAX_BYTE_LANES; ByteLane++)
|
||||
{
|
||||
if (pDCTData->Status[DCT_STATUS_REGISTERED])
|
||||
RegisterDelay = 0x20; /* TODO: ((RCW2 & BIT0) == 0) ? 0x20 : 0x30; */
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if (pDCTData->Status[DCT_STATUS_REGISTERED]) {
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if (AddrCmdPrelaunch == 0)
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RegisterDelay = 0x20;
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else
|
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RegisterDelay = 0x30;
|
||||
} else {
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||||
RegisterDelay = 0;
|
||||
SeedTotal = (pDCTData->WLFineDelay[MAX_BYTE_LANES*dimm+ByteLane] & 0x1f) |
|
||||
(pDCTData->WLGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] << 5);
|
||||
}
|
||||
SeedTotalPreScaling = ((pDCTData->WLFineDelay[MAX_BYTE_LANES*dimm+ByteLane] & 0x1f) |
|
||||
(pDCTData->WLGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] << 5)) - RegisterDelay;
|
||||
/* SeedTotalPreScaling = (the total delay value in F2x[1, 0]9C_x[4A:30] from pass 1 of write levelization
|
||||
training) - RegisterDelay. */
|
||||
SeedTotal = (uint16_t) (RegisterDelay + ((((uint64_t) SeedTotal - RegisterDelay) *
|
||||
fam10h_freq_tab[MemClkFreq-3] * 100) / (fam10h_freq_tab[0] * 100)));
|
||||
SeedTotal = (uint16_t) ((((uint64_t) SeedTotalPreScaling) *
|
||||
fam10h_freq_tab[MemClkFreq] * 100) / (fam10h_freq_tab[3] * 100));
|
||||
Seed_Gross = SeedTotal / 32;
|
||||
Seed_Fine = SeedTotal & 0x1f;
|
||||
if (Seed_Gross == 0)
|
||||
|
|
@ -1201,8 +1210,20 @@ void procConfig(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, ui
|
|||
Seed_Gross = 1;
|
||||
else
|
||||
Seed_Gross = 2;
|
||||
|
||||
/* The BKDG-recommended algorithm causes problems with registered DIMMs on some systems
|
||||
* due to the long register delays causing premature total delay wrap-around.
|
||||
* Attempt to work around this...
|
||||
*/
|
||||
SeedTotal = ((Seed_Gross & 0x1f) << 5) | (Seed_Fine & 0x1f);
|
||||
SeedTotal += RegisterDelay;
|
||||
Seed_Gross = SeedTotal / 32;
|
||||
Seed_Fine = SeedTotal & 0x1f;
|
||||
|
||||
pDCTData->WLGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_Gross;
|
||||
pDCTData->WLFineDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_Fine;
|
||||
|
||||
printk(BIOS_SPEW, "\tLane %02x new seed: %04x\n", ByteLane, ((Seed_Gross & 0x1f) << 5) | (Seed_Fine & 0x1f));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1379,6 +1400,8 @@ void getWLByteDelay(struct DCTStatStruc *pDCTstat, uint8_t dct, u8 ByteLane, u8
|
|||
gross = get_ADD_DCT_Bits(pDCTData, dct, pDCTData->NodeId,
|
||||
FUN_DCT, (u16)addr, grossStartLoc, grossEndLoc);
|
||||
|
||||
printk(BIOS_SPEW, "\tLane %02x raw readback: %04x\n", ByteLane, ((gross & 0x1f) << 5) | (fine & 0x1f));
|
||||
|
||||
if (!is_fam15h()) {
|
||||
/* Adjust seed gross delay overflow (greater than 3):
|
||||
* - Adjust the trained gross delay to the original seed gross delay.
|
||||
|
|
@ -1402,4 +1425,5 @@ void getWLByteDelay(struct DCTStatStruc *pDCTstat, uint8_t dct, u8 ByteLane, u8
|
|||
}
|
||||
pDCTData->WLFineDelay[index+ByteLane] = (u8)fine;
|
||||
pDCTData->WLGrossDelay[index+ByteLane] = (u8)gross;
|
||||
printk(BIOS_SPEW, "\tLane %02x final adjusted value: %04x\n", ByteLane, ((gross & 0x1f) << 5) | (fine & 0x1f));
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue