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mb/amd/birman/gpio: Change non-GEvent GPIOs to PAD_INT 

Two GPIOs were set as SCI, but are not GEvent capable pins on morgana.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I00dc1b2595c047ce6898b394061d119ac8680755
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Fred Reitberger 2022-12-02 16:03:05 -05:00 committed by Felix Held
parent 5d029bbb90
commit f68bd1273b
2 changed files with 3 additions and 3 deletions
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2
src/mainboard/amd/birman/early_gpio.c
View File

@ -23,7 +23,7 @@ static const struct soc_amd_gpio gpio_set_stage_reset[] = {
/* ESPI_ALERT_L */
PAD_NF(GPIO_22, ESPI_ALERT_D1, PULL_NONE),
/* TPM IRQ */
PAD_SCI(GPIO_130, PULL_UP, EDGE_LOW),
PAD_INT(GPIO_130, PULL_NONE, EDGE_LOW, STATUS_DELIVERY),
/* SPI_ROM_REQ */
PAD_NF(GPIO_67, SPI_ROM_REQ, PULL_NONE),
/* SPI_ROM_GNT */

4
src/mainboard/amd/birman/gpio.c
View File

@ -65,7 +65,7 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
/* ESPI_CS_L */
PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE),
/* INT_CLKREQ_L */
PAD_SCI(GPIO_31, PULL_UP, EDGE_LOW),
PAD_INT(GPIO_31, PULL_NONE, EDGE_LOW, STATUS_DELIVERY),
/* LPC_RST_L */
PAD_NF(GPIO_32, LPC_RST_L, PULL_NONE),
/* GPIO_33 - GPIO_37: Not available */
@ -138,7 +138,7 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
PAD_NF(GPIO_116, CLK_REQ2_L, PULL_NONE),
/* GPIO_117 - GPIO_129: Not available */
/* TPM IRQ */
PAD_SCI(GPIO_130, PULL_UP, EDGE_LOW),
PAD_INT(GPIO_130, PULL_NONE, EDGE_LOW, STATUS_DELIVERY),
/* CLK_REQ3_L */
PAD_NF(GPIO_131, CLK_REQ3_L, PULL_NONE),
/* CLK_REQ4_L */